mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-01-09 03:38:52 +00:00
e6a8c6f5c0
Add pe2201 platform code and the device tree of pe2201 platform board.
The initial support comprises the UART and PCIe.
Signed-off-by: TracyMg_Li <TracyMg_Li@outlook.com>
Changes since v1:
fix space corrupt.
Changes since v2:
switch to bootstd and text environment.
Changes since v3:
add environment variables.
75 lines
1.3 KiB
C
75 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023, Phytium Technology Co., Ltd.
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* lixinde <lixinde@phytium.com.cn>
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* weichangzheng <weichangzheng@phytium.com.cn>
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*/
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#include <stdio.h>
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#include <string.h>
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#include <asm/io.h>
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#include <linux/arm-smccc.h>
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#include <init.h>
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#include "cpu.h"
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struct pll_config {
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u32 magic;
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u32 version;
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u32 size;
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u8 rev1[4];
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u32 clust0_pll;
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u32 clust1_pll;
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u32 clust2_pll;
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u32 noc_pll;
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u32 dmu_pll;
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} __attribute((aligned(4)));
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struct pll_config const pll_base_info = {
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.magic = PARAMETER_PLL_MAGIC,
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.version = 0x2,
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.size = 0x100,
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.clust0_pll = 2000,
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.clust1_pll = 2000,
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.clust2_pll = 2000,
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.noc_pll = 1800,
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.dmu_pll = 600,
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};
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u32 get_reset_source(void)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res);
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return res.a0;
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}
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void pll_init(void)
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{
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u8 buffer[0x100];
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struct arm_smccc_res res;
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memcpy(buffer, &pll_base_info, sizeof(pll_base_info));
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arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
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if (res.a0 != 0)
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panic("PLL init failed :0x%lx\n", res.a0);
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}
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void check_reset(void)
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{
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u32 rst;
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rst = get_reset_source();
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switch (rst) {
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case CPU_RESET_POWER_ON:
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pll_init();
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break;
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case CPU_RESET_PLL:
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break;
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case CPU_RESET_WATCH_DOG:
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break;
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default:
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panic("other reset source\n");
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}
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}
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