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ARM add initial support for the Phytium Pe2201 Board.

Browse source 
Add pe2201 platform code and the device tree of pe2201 platform board.
The initial support comprises the UART and PCIe.

Signed-off-by: TracyMg_Li <TracyMg_Li@outlook.com>
Changes since v1:
        fix space corrupt.
Changes since v2:
        switch to bootstd and text environment.
Changes since v3:
        add environment variables.
This commit is contained in:
TracyMg_Li 2023-12-25 11:21:34 +08:00 committed by Tom Rini
parent ddcfb9ede8
commit e6a8c6f5c0
15 changed files with 684 additions and 0 deletions
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7
arch/arm/Kconfig
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@ -2071,6 +2071,12 @@ config TARGET_POMELO
Support for pomelo platform.
It has 8GB Sdram, uart and pcie.
config TARGET_PE2201
bool "Support Phytium PE2201 Platform"
select ARM64
help
Support for pe2201 platform.It has 2GB Sdram, uart and pcie.
config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
@ -2347,6 +2353,7 @@ source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/phytium/durian/Kconfig"
source "board/phytium/pomelo/Kconfig"
source "board/phytium/pe2201/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"
source "arch/arm/Kconfig.debug"

1
arch/arm/dts/Makefile
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@ -1480,6 +1480,7 @@ dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
dtb-$(CONFIG_TARGET_PE2201) += phytium-pe2201.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb

43
arch/arm/dts/phytium-pe2201.dts Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Phytium pe2201 board
* Copyright (C) 2023, Phytium Technology Co., Ltd.
* lixinde <lixinde@phytium.com.cn>
* weichangzheng <weichangzheng@phytium.com.cn>
*/
/dts-v1/;
/ {
model = "Phytium pe2201 Board";
compatible = "phytium,pe2201";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
};
uart0: serial@2800c000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x2800c000 0x0 0x1000>;
clock = <100000000>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie@40000000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x40000000 0x0 0x10000000>;
ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>,
<0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,
<0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
};
};
};

12
board/phytium/pe2201/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_PE2201
config SYS_BOARD
default "pe2201"
config SYS_VENDOR
default "phytium"
config SYS_CONFIG_NAME
default "pe2201"
endif

8
board/phytium/pe2201/MAINTAINERS Normal file
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@ -0,0 +1,8 @@
PE2201 BOARD
M: lixinde <lixinde@phytium.com.cn>
M: weichangzheng <weichangzheng@phytium.com.cn>
S: Maintained
F: board/phytium/pe2201/*
F: include/configs/pe2201.h
F: configs/pe2201_defconfig
F: arch/arm/dts/phytium-pe2201.dts

12
board/phytium/pe2201/Makefile Normal file
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@ -0,0 +1,12 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2023, Phytium Technology Co., Ltd.
# lixinde <lixinde@phytium.com.cn>
# weichangzheng <weichangzheng@phytium.com.cn>
#
obj-y += pe2201.o
obj-y += pll.o
obj-y += pcie.o
obj-y += ddr.o
obj-y += sec.o

64
board/phytium/pe2201/cpu.h Normal file
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@ -0,0 +1,64 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2023, Phytium Technology Co., Ltd.
* lixinde <lixinde@phytium.com.cn>
* weichangzheng <weichangzheng@phytium.com.cn>
*/
#ifndef _FT_PE2201_H
#define _FT_PE2201_H
/* SMCCC ID */
#define CPU_SVC_VERSION 0xC2000F00
#define CPU_GET_RST_SOURCE 0xC2000F01
#define CPU_INIT_PLL 0xC2000F02
#define CPU_INIT_PCIE 0xC2000F03
#define CPU_INIT_MEM 0xC2000F04
#define CPU_INIT_SEC_SVC 0xC2000F05
/* CPU RESET */
#define CPU_RESET_POWER_ON 0x1
#define CPU_RESET_PLL 0x4
#define CPU_RESET_WATCH_DOG 0x8
/* PLL */
#define PARAMETER_PLL_MAGIC 0x54460020
/* PCIE */
#define PARAMETER_PCIE_MAGIC 0x54460021
#define CFG_INDEPENDENT_TREE 0x0
#define PCI_PEU0 0x1
#define PCI_PEU1 0x1
#define PEU1_OFFSET 16
#define PEU_C_OFFSET_MODE 16
#define PEU_C_OFFSET_SPEED 0
#define X1X1X1X1 0x2
#define X1X1 0x0
#define EP_MODE 0x0
#define RC_MODE 0x1
#define GEN3 3
/* DDR */
#define PARAMETER_MCU_MAGIC 0x54460024
#define PARAM_MCU_VERSION 0x3
#define PARAM_MCU_SIZE 0x100
#define PARAM_CH_ENABLE 0x1
#define RDIMM_TYPE 0x1
#define UDIMM_TYPE 0x2
#define LPDDR4_TYPE 0x10
#define DIMM_X8 0x1
#define DIMM_X16 0x2
#define NO_MIRROR 0x0
#define NO_ECC_TYPE 0
#define DDR4_TYPE 0xC
/* SEC */
#define PARAMETER_COMMON_MAGIC 0x54460013
void ddr_init(void);
void sec_init(void);
void check_reset(void);
void pcie_init(void);
#endif /* _FT_PE2201_H */

190
board/phytium/pe2201/ddr.c Normal file
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@ -0,0 +1,190 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023, Phytium Technology Co., Ltd.
* lixinde <lixinde@phytium.com.cn>
* weichangzheng <weichangzheng@phytium.com.cn>
*/
#include <stdio.h>
#include <linux/arm-smccc.h>
#include <init.h>
#include "cpu.h"
struct ddr_spd {
/***************** read from spd ******************/
u8 dimm_type; /* 1: RDIMM; 2: UDIMM; 3: SODIMM; 4: LRDIMM */
u8 data_width; /* 0: x4; 1: x8; 2: x16; 3: x32 */
u8 mirror_type; /* 0: standard; 1: mirror */
u8 ecc_type; /* 0: no-ecc; 1: ecc */
u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */
u8 rank_num;
u8 row_num;
u8 col_num;
u8 bg_num; /* DDR4/DDR5 */
u8 bank_num;
u16 module_manufacturer_id;
u16 taamin;
u16 trcdmin;
u16 trpmin;
u16 trasmin;
u16 trcmin;
u16 tfawmin; /* only DDR3/DDR4 */
u16 trrd_smin; /* only DDR4 */
u16 trrd_lmin; /* only DDR4 */
u16 tccd_lmin; /* only DDR4 */
u16 twrmin;
u16 twtr_smin; /* only DDR4 */
u16 twtr_lmin; /* only DDR4 */
u32 trfc1min;
u32 trfc2min;
u32 trfc4_rfcsbmin; /* DDR4: tRFC4min; DDR5: tRFCsbmin */
u8 resv[8];
/***************** RCD control words ******************/
u8 f0rc03; /* bit[3:2]:CS bit[1:0]:CA */
u8 f0rc04; /* bit[3:2]:ODT bit[1:0]:CKE */
u8 f0rc05; /* bit[3:2]:CLK-A side bit[1:0]:CLK-B side */
u8 rcd_num; /* Registers used on RDIMM */
u8 lrdimm_resv[4];
u8 lrdimm_resv1[8];
u8 lrdimm_resv2[8];
} __attribute((aligned(4)));
struct mcu_config {
u32 magic;
u32 version;
u32 size;
u8 rev1[4];
u8 ch_enable;
u8 resv1[7];
u64 misc_enable;
u8 train_debug;
u8 train_recover;
u8 train_param_type;
u8 train_param_1; /* DDR4: cpu_odt */
u8 train_param_2; /* DDR4: cpu_drv */
u8 train_param_3; /* DDR4: mr_drv */
u8 train_param_4; /* DDR4: rtt_nom */
u8 train_param_5; /* DDR4: rtt_park */
u8 train_param_6; /* DDR4: rtt_wr */
u8 resv2[7];
/***************** for LPDDR4 dq swap ******************/
u32 data_byte_swap;
u32 slice0_dq_swizzle;
u32 slice1_dq_swizzle;
u32 slice2_dq_swizzle;
u32 slice3_dq_swizzle;
u32 slice4_dq_swizzle;
u32 slice5_dq_swizzle;
u32 slice6_dq_swizzle;
u32 slice7_dq_swizzle;
u8 resv3[4];
u8 resv4[8];
struct ddr_spd ddr_spd_info;
} __attribute((aligned(4)));
static void get_mcu_up_info_default(struct mcu_config *pm)
{
pm->magic = PARAMETER_MCU_MAGIC;
pm->version = PARAM_MCU_VERSION;
pm->size = PARAM_MCU_SIZE;
pm->ch_enable = PARAM_CH_ENABLE;
}
static u8 init_dimm_param(struct mcu_config *pm)
{
debug("manual config dimm info...\n");
pm->misc_enable = 0x2001;
pm->train_debug = 0x0;
pm->train_recover = 0x0;
pm->train_param_type = 0x0;
pm->train_param_1 = 0x0;
pm->train_param_2 = 0x0;
pm->train_param_3 = 0x0;
pm->train_param_4 = 0x0;
pm->train_param_5 = 0x0;
pm->train_param_6 = 0x0;
pm->data_byte_swap = 0x76543210;
pm->slice0_dq_swizzle = 0x3145726;
pm->slice1_dq_swizzle = 0x54176230;
pm->slice2_dq_swizzle = 0x57604132;
pm->slice3_dq_swizzle = 0x20631547;
pm->slice4_dq_swizzle = 0x16057423;
pm->slice5_dq_swizzle = 0x16057423;
pm->slice6_dq_swizzle = 0x16057423;
pm->slice7_dq_swizzle = 0x16057423;
pm->ddr_spd_info.dimm_type = RDIMM_TYPE;
pm->ddr_spd_info.data_width = DIMM_X16;
pm->ddr_spd_info.mirror_type = NO_MIRROR;
pm->ddr_spd_info.ecc_type = NO_ECC_TYPE;
pm->ddr_spd_info.dram_type = LPDDR4_TYPE;
pm->ddr_spd_info.rank_num = 0x1;
pm->ddr_spd_info.row_num = 0x10;
pm->ddr_spd_info.col_num = 0xa;
pm->ddr_spd_info.bg_num = 0x0;
pm->ddr_spd_info.bank_num = 0x8;
pm->ddr_spd_info.taamin = 0x0;
pm->ddr_spd_info.trcdmin = 0x0;
pm->ddr_spd_info.trpmin = 0x0;
pm->ddr_spd_info.trasmin = 0x0;
pm->ddr_spd_info.trcmin = 0x0;
pm->ddr_spd_info.tfawmin = 0x0;
pm->ddr_spd_info.trrd_smin = 0x0;
pm->ddr_spd_info.trrd_lmin = 0x0;
pm->ddr_spd_info.tccd_lmin = 0x0;
pm->ddr_spd_info.twrmin = 0x0;
pm->ddr_spd_info.twtr_smin = 0x0;
pm->ddr_spd_info.twtr_lmin = 0x0;
return 0;
}
void get_default_mcu_info(u8 *data)
{
get_mcu_up_info_default((struct mcu_config *)data);
}
void fix_mcu_info(u8 *data)
{
struct mcu_config *mcu_info = (struct mcu_config *)data;
init_dimm_param(mcu_info);
}
void ddr_init(void)
{
u8 buffer[0x100];
struct arm_smccc_res res;
get_default_mcu_info(buffer);
fix_mcu_info(buffer);
arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
if (res.a0 != 0)
panic("DRAM init failed :0x%lx\n", res.a0);
}

60
board/phytium/pe2201/pcie.c Normal file
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@ -0,0 +1,60 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023, Phytium Technology Co., Ltd.
* lixinde <lixinde@phytium.com.cn>
* weichangzheng <weichangzheng@phytium.com.cn>
*/
#include <stdio.h>
#include <string.h>
#include <linux/arm-smccc.h>
#include <init.h>
#include "cpu.h"
struct pcu_ctr {
u32 base_config[4];
u32 equalization[4];
u8 rev[72];
} __attribute((aligned(4)));
struct pcu_config {
u32 magic;
u32 version;
u32 size;
u8 rev1[4];
u32 independent_tree;
u32 base_cfg;
u8 rev2[16];
struct pcu_ctr ctr_cfg[2];
} __attribute((aligned(4)));
struct pcu_config const peu_base_info = {
.magic = PARAMETER_PCIE_MAGIC,
.version = 0x4,
.size = 0x100,
.independent_tree = CFG_INDEPENDENT_TREE,
.base_cfg = ((PCI_PEU1 | (X1X1X1X1 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X1X1 << 1))),
.ctr_cfg[0].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
.ctr_cfg[0].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
.ctr_cfg[0].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
.ctr_cfg[1].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
.ctr_cfg[1].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
.ctr_cfg[1].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
.ctr_cfg[0].equalization[0] = 0x7,
.ctr_cfg[0].equalization[1] = 0x7,
.ctr_cfg[0].equalization[2] = 0x7,
.ctr_cfg[1].equalization[0] = 0x7,
.ctr_cfg[1].equalization[1] = 0x7,
.ctr_cfg[1].equalization[2] = 0x7,
};
void pcie_init(void)
{
u8 buffer[0x100];
struct arm_smccc_res res;
memcpy(buffer, &peu_base_info, sizeof(peu_base_info));
arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
if (res.a0 != 0)
panic("PCIE init failed :0x%lx\n", res.a0);
}

92
board/phytium/pe2201/pe2201.c Normal file
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@ -0,0 +1,92 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023, Phytium Technology Co., Ltd.
* lixinde <lixinde@phytium.com.cn>
* weichangzheng <weichangzheng@phytium.com.cn>
*/
#include <stdio.h>
#include <command.h>
#include <init.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <linux/arm-smccc.h>
#include <scsi.h>
#include <asm/u-boot.h>
#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR;
int mach_cpu_init(void)
{
check_reset();
return 0;
}
int board_early_init_f(void)
{
pcie_init();
return 0;
}
int dram_init(void)
{
debug("Phytium ddr init\n");
ddr_init();
gd->mem_clk = 0;
gd->ram_size = PHYS_SDRAM_1_SIZE;
sec_init();
debug("PBF relocate done\n");
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
int board_init(void)
{
return 0;
}
void reset_cpu(void)
{
struct arm_smccc_res res;
debug("run in reset cpu\n");
arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
if (res.a0 != 0)
panic("reset cpu error, %lx\n", res.a0);
}
static struct mm_region pe2201_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN
},
{
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x7b000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NS | PTE_BLOCK_INNER_SHARE
},
{
0,
}
};
struct mm_region *mem_map = pe2201_mem_map;
int last_stage_init(void)
{
return 0;
}

25
board/phytium/pe2201/pe2201.env Normal file
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@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023, Phytium Technology Co., Ltd.
*/
/* Initial environment variables */
image=Image
scriptaddr=0x90100000
script_offset_f=0xc00000
script_size_f=0x2000
kernel_addr_r=0x90200000
fdt_addr_r=0x90000000
boot_fit=no
fdtfile=phytium-pe2201.dtb
ft_fdt_name=boot/dtb/pe2201.dtb
fdtoverlay_addr_r=0x95100000
kernel_comp_addr_r=0x96000000
kernel_comp_size=0x2000000
pxefile_addr_r=0x9A000000
ramdisk_addr_r=0x95000000
load_kernel=ext4load scsi 0:2 $kernel_addr_r boot/uImage-2004
load_initrd=ext4load scsi 0:2 $ramdisk_addr_r initrd.img-4.19.0.pe2201
load_fdt=ext4load scsi 0:2 $fdt_addr_r $ft_fdt_name
distro_bootcmd=run load_kernel; run load_initrd; run load_fdt; run boot_os

75
board/phytium/pe2201/pll.c Normal file
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@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023, Phytium Technology Co., Ltd.
* lixinde <lixinde@phytium.com.cn>
* weichangzheng <weichangzheng@phytium.com.cn>
*/
#include <stdio.h>
#include <string.h>
#include <asm/io.h>
#include <linux/arm-smccc.h>
#include <init.h>
#include "cpu.h"
struct pll_config {
u32 magic;
u32 version;
u32 size;
u8 rev1[4];
u32 clust0_pll;
u32 clust1_pll;
u32 clust2_pll;
u32 noc_pll;
u32 dmu_pll;
} __attribute((aligned(4)));
struct pll_config const pll_base_info = {
.magic = PARAMETER_PLL_MAGIC,
.version = 0x2,
.size = 0x100,
.clust0_pll = 2000,
.clust1_pll = 2000,
.clust2_pll = 2000,
.noc_pll = 1800,
.dmu_pll = 600,
};
u32 get_reset_source(void)
{
struct arm_smccc_res res;
arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res);
return res.a0;
}
void pll_init(void)
{
u8 buffer[0x100];
struct arm_smccc_res res;
memcpy(buffer, &pll_base_info, sizeof(pll_base_info));
arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
if (res.a0 != 0)
panic("PLL init failed :0x%lx\n", res.a0);
}
void check_reset(void)
{
u32 rst;
rst = get_reset_source();
switch (rst) {
case CPU_RESET_POWER_ON:
pll_init();
break;
case CPU_RESET_PLL:
break;
case CPU_RESET_WATCH_DOG:
break;
default:
panic("other reset source\n");
}
}

37
board/phytium/pe2201/sec.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023, Phytium Technology Co., Ltd.
* lixinde <lixinde@phytium.com.cn>
* weichangzheng <weichangzheng@phytium.com.cn>
*/
#include <stdio.h>
#include <string.h>
#include <linux/arm-smccc.h>
#include <init.h>
#include "cpu.h"
struct common_config {
u32 magic;
u32 version;
u32 size;
u8 rev1[4];
u64 core_bit_map;
} __attribute((aligned(4)));
struct common_config const common_base_info = {
.magic = PARAMETER_COMMON_MAGIC,
.version = 0x1,
.core_bit_map = 0x3333,
};
void sec_init(void)
{
u8 buffer[0x100];
struct arm_smccc_res res;
memcpy(buffer, &common_base_info, sizeof(common_base_info));
arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
if (res.a0 != 0)
panic("SEC init failed :0x%lx\n", res.a0);
}

42
configs/pe2201_defconfig Normal file
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@ -0,0 +1,42 @@
CONFIG_ARM=y
CONFIG_ARM_SMCCC=y
CONFIG_TARGET_PE2201=y
CONFIG_TEXT_BASE=0x38180000
CONFIG_SYS_MALLOC_LEN=0x101000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30c1a000
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="phytium-pe2201"
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_PSCI_RESET is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon=pl011,0x2800c000 root=/dev/sda2 rw"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_PROMPT="pe2201#"
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_PCI=y
CONFIG_CMD_DM=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_PHYTIUM=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_CMD_BOOTMETH=y

16
include/configs/pe2201.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2023, Phytium Technology Co., Ltd.
* lixinde <lixinde@phytium.com.cn>
* weichangzheng <weichangzheng@phytium.com.cn>
*/
#ifndef __PE2201_CONFIG_H
#define __PE2201_CONFIG_H
/* SDRAM Bank #1 start address */
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE 0x74000000
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#endif