mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-01-23 18:35:11 +00:00
e6a8c6f5c0
Add pe2201 platform code and the device tree of pe2201 platform board.
The initial support comprises the UART and PCIe.
Signed-off-by: TracyMg_Li <TracyMg_Li@outlook.com>
Changes since v1:
fix space corrupt.
Changes since v2:
switch to bootstd and text environment.
Changes since v3:
add environment variables.
64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2023, Phytium Technology Co., Ltd.
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* lixinde <lixinde@phytium.com.cn>
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* weichangzheng <weichangzheng@phytium.com.cn>
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*/
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#ifndef _FT_PE2201_H
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#define _FT_PE2201_H
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/* SMCCC ID */
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#define CPU_SVC_VERSION 0xC2000F00
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#define CPU_GET_RST_SOURCE 0xC2000F01
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#define CPU_INIT_PLL 0xC2000F02
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#define CPU_INIT_PCIE 0xC2000F03
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#define CPU_INIT_MEM 0xC2000F04
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#define CPU_INIT_SEC_SVC 0xC2000F05
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/* CPU RESET */
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#define CPU_RESET_POWER_ON 0x1
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#define CPU_RESET_PLL 0x4
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#define CPU_RESET_WATCH_DOG 0x8
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/* PLL */
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#define PARAMETER_PLL_MAGIC 0x54460020
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/* PCIE */
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#define PARAMETER_PCIE_MAGIC 0x54460021
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#define CFG_INDEPENDENT_TREE 0x0
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#define PCI_PEU0 0x1
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#define PCI_PEU1 0x1
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#define PEU1_OFFSET 16
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#define PEU_C_OFFSET_MODE 16
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#define PEU_C_OFFSET_SPEED 0
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#define X1X1X1X1 0x2
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#define X1X1 0x0
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#define EP_MODE 0x0
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#define RC_MODE 0x1
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#define GEN3 3
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/* DDR */
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#define PARAMETER_MCU_MAGIC 0x54460024
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#define PARAM_MCU_VERSION 0x3
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#define PARAM_MCU_SIZE 0x100
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#define PARAM_CH_ENABLE 0x1
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#define RDIMM_TYPE 0x1
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#define UDIMM_TYPE 0x2
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#define LPDDR4_TYPE 0x10
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#define DIMM_X8 0x1
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#define DIMM_X16 0x2
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#define NO_MIRROR 0x0
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#define NO_ECC_TYPE 0
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#define DDR4_TYPE 0xC
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/* SEC */
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#define PARAMETER_COMMON_MAGIC 0x54460013
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void ddr_init(void);
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void sec_init(void);
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void check_reset(void);
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void pcie_init(void);
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#endif /* _FT_PE2201_H */
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