Lokesh Vutla 4d790788ce ARM: dra7xx: Change DPLL_PER_HS13 divider value ... According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz clock, so that driver can use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>		2016-07-30 00:15:00 +05:30
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abb.c	DRA7: add ABB setup for MPU voltage domain	2014-01-24 11:41:17 -05:00
boot.c	omap5: Definitions for SYS_BOOT-based fallback boot device selection	2015-07-27 15:02:09 -04:00
config.mk	arm: omap5: fix build dependency for secure devices	2016-07-22 14:46:26 -04:00
dra7xx_iodelay.c	ARM: OMAP5/DRA7: Expose do_set_iodelay	2016-03-27 09:12:15 -04:00
emif.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
fdt.c	ARM: omap5: add hooks for cpu/SoC fdt fixups	2016-05-27 15:41:37 -04:00
hw_data.c	ARM: dra7xx: Change DPLL_PER_HS13 divider value	2016-07-30 00:15:00 +05:30
hwinit.c	ARM: DRA72x: Add support for detection of SR2.0	2016-03-27 09:12:12 -04:00
Kconfig	board: am57xx: Rename TARGET_BEAGLE_X15 as TARGET_AM57XX_EVM	2016-06-13 08:56:36 -04:00
Makefile	ARM: omap5: add hooks for cpu/SoC fdt fixups	2016-05-27 15:41:37 -04:00
prcm-regs.c	dra7xx: Enable USB_PHY3 32KHz clock	2016-06-02 21:42:15 -04:00
sdram.c	ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0	2016-03-27 09:12:14 -04:00