mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-24 08:22:14 +00:00
189ec2fee6
Device tree alignment with Linux kernel v5.18-rc2: - ARM: dts: stm32: Add support for the emtrion emSBC-Argon (only the pincontrol part) - ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node - ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151 - ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15 - ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on stm32mp157 - ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151 - ARM: dts: stm32: keep uart4 behavior on * - ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
247 lines
3 KiB
Text
247 lines
3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
/*
|
|
* Copyright : STMicroelectronics 2018
|
|
*/
|
|
|
|
/ {
|
|
aliases {
|
|
gpio0 = &gpioa;
|
|
gpio1 = &gpiob;
|
|
gpio2 = &gpioc;
|
|
gpio3 = &gpiod;
|
|
gpio4 = &gpioe;
|
|
gpio5 = &gpiof;
|
|
gpio6 = &gpiog;
|
|
gpio7 = &gpioh;
|
|
gpio8 = &gpioi;
|
|
gpio9 = &gpioj;
|
|
gpio10 = &gpiok;
|
|
gpio25 = &gpioz;
|
|
pinctrl0 = &pinctrl;
|
|
pinctrl1 = &pinctrl_z;
|
|
};
|
|
|
|
binman: binman {
|
|
multiple-images;
|
|
};
|
|
|
|
clocks {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
/* need PSCI for sysreset during board_f */
|
|
psci {
|
|
u-boot,dm-pre-proper;
|
|
};
|
|
|
|
reboot {
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "syscon-reboot";
|
|
regmap = <&rcc>;
|
|
offset = <0x404>;
|
|
mask = <0x1>;
|
|
};
|
|
|
|
soc {
|
|
u-boot,dm-pre-reloc;
|
|
|
|
ddr: ddr@5a003000 {
|
|
u-boot,dm-pre-reloc;
|
|
|
|
compatible = "st,stm32mp1-ddr";
|
|
|
|
reg = <0x5a003000 0x550
|
|
0x5a004000 0x234>;
|
|
|
|
clocks = <&rcc AXIDCG>,
|
|
<&rcc DDRC1>,
|
|
<&rcc DDRC2>,
|
|
<&rcc DDRPHYC>,
|
|
<&rcc DDRCAPB>,
|
|
<&rcc DDRPHYCAPB>;
|
|
|
|
clock-names = "axidcg",
|
|
"ddrc1",
|
|
"ddrc2",
|
|
"ddrphyc",
|
|
"ddrcapb",
|
|
"ddrphycapb";
|
|
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
&bsec {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&clk_csi {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&clk_hsi {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&clk_hse {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&clk_lsi {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&clk_lse {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&cpu0_opp_table {
|
|
u-boot,dm-spl;
|
|
opp-650000000 {
|
|
u-boot,dm-spl;
|
|
};
|
|
opp-800000000 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&gpioa {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiob {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioc {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiod {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioe {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiof {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiog {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioh {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioi {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioj {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiok {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioz {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&iwdg2 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
/* pre-reloc probe = reserve video frame buffer in video_reserve() */
|
|
<dc {
|
|
u-boot,dm-pre-proper;
|
|
};
|
|
|
|
/* temp = waiting kernel update */
|
|
&m4_rproc {
|
|
resets = <&rcc MCU_R>,
|
|
<&rcc MCU_HOLD_BOOT_R>;
|
|
reset-names = "mcu_rst", "hold_boot";
|
|
};
|
|
|
|
&pinctrl {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&pinctrl_z {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&pwr_regulators {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&rcc {
|
|
u-boot,dm-pre-reloc;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
&usart1 {
|
|
resets = <&rcc USART1_R>;
|
|
};
|
|
|
|
&usart2 {
|
|
resets = <&rcc USART2_R>;
|
|
};
|
|
|
|
&usart3 {
|
|
resets = <&rcc USART3_R>;
|
|
};
|
|
|
|
&uart4 {
|
|
resets = <&rcc UART4_R>;
|
|
};
|
|
|
|
&uart5 {
|
|
resets = <&rcc UART5_R>;
|
|
};
|
|
|
|
&usart6 {
|
|
resets = <&rcc USART6_R>;
|
|
};
|
|
|
|
&uart7 {
|
|
resets = <&rcc UART7_R>;
|
|
};
|
|
|
|
&uart8{
|
|
resets = <&rcc UART8_R>;
|
|
};
|
|
|
|
#if defined(CONFIG_STM32MP15x_STM32IMAGE)
|
|
&binman {
|
|
u-boot-stm32 {
|
|
filename = "u-boot.stm32";
|
|
mkimage {
|
|
args = "-T stm32image -a 0xc0100000 -e 0xc0100000";
|
|
u-boot {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_SPL)
|
|
&binman {
|
|
spl-stm32 {
|
|
filename = "u-boot-spl.stm32";
|
|
mkimage {
|
|
args = "-T stm32image -a 0x2ffc2500 -e 0x2ffc2500";
|
|
u-boot-spl {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
#endif
|