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u-boot/arch/mips
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Daniel Schwierzeck b838586086 MIPS: cache: optimise changing of k0 CCA mode 
Changing the Cache Coherency Algorithm (CCA) for kernel mode
requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1
before changing the CCA mode. Jump back to KSEG0 afterwards.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 21:02:03 +02:00
..
cpu MIPS: start.S: make boot config at offset 0x10 configurable 2018-09-22 20:59:22 +02:00
dts dt: bcm6838: add pinctrl 2018-09-22 20:49:59 +02:00
include/asm arch: types.h: factor out fixed width typedefs to int-ll64.h 2018-09-10 20:48:16 -04:00
lib MIPS: cache: optimise changing of k0 CCA mode 2018-09-22 21:02:03 +02:00
mach-ath79 Kconfig: Sort bool, default, select and imply options 2018-07-30 07:18:48 -04:00
mach-bmips bcm968380gerg: add initial support 2018-08-08 13:38:17 +02:00
mach-pic32 Kconfig: Sort bool, default, select and imply options 2018-07-30 07:18:48 -04:00
config.mk SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
Kconfig MIPS: start.S: make boot config at offset 0x10 configurable 2018-09-22 20:59:22 +02:00
Makefile mips: au1x00: Remove support for these SoCs 2018-08-08 13:34:27 +02:00
Makefile.postlink SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00