mirror of
https://github.com/AsahiLinux/u-boot
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7ae8350f67
Currently in some cases SDRAM init requires global_data to be available and soon this will not be available prior to board_init_f(). Adjust the code paths in these cases to be correct. In some cases we had the SPL stack be in DDR as we might have large stacks (due to Falcon Mode + Environment). In these cases switch to CONFIG_SPL_STACK_R. In other cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also in SRAM) so drop those lines. Signed-off-by: Simon Glass <sjg@chromium.org> Tested on Beagleboard, Beagleboard xM Tested-by: Matt Porter <mporter@konsulko.com> Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
257 lines
5.2 KiB
C
257 lines
5.2 KiB
C
/*
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*
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* Common functions for OMAP4/5 based boards
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/sizes.h>
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#include <asm/emif.h>
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#include <asm/omap_common.h>
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#include <linux/compiler.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
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{
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int i;
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struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
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for (i = 0; i < size; i++, pad++)
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writew(pad->val, base + pad->offset);
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}
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static void set_mux_conf_regs(void)
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{
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switch (omap_hw_init_context()) {
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case OMAP_INIT_CONTEXT_SPL:
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set_muxconf_regs_essential();
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break;
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case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
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break;
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case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
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case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
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set_muxconf_regs_essential();
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break;
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}
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}
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u32 cortex_rev(void)
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{
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unsigned int rev;
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/* Read Main ID Register (MIDR) */
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asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
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return rev;
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}
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static void omap_rev_string(void)
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{
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u32 omap_rev = omap_revision();
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u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
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u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
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u32 major_rev = (omap_rev & 0x00000F00) >> 8;
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u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
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if (soc_variant)
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printf("OMAP");
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else
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printf("DRA");
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printf("%x ES%x.%x\n", omap_variant, major_rev,
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minor_rev);
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}
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#ifdef CONFIG_SPL_BUILD
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void spl_display_print(void)
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{
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omap_rev_string();
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}
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#endif
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void __weak srcomp_enable(void)
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{
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}
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#ifdef CONFIG_ARCH_CPU_INIT
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/*
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* SOC specific cpu init
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*/
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int arch_cpu_init(void)
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{
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save_omap_boot_params();
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return 0;
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}
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#endif /* CONFIG_ARCH_CPU_INIT */
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/*
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* Routine: s_init
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* Description: Does early system init of watchdog, muxing, andclocks
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* Watchdog disable is done always. For the rest what gets done
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* depends on the boot mode in which this function is executed
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* 1. s_init of SPL running from SRAM
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* 2. s_init of U-Boot running from FLASH
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* 3. s_init of U-Boot loaded to SDRAM by SPL
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* 4. s_init of U-Boot loaded to SDRAM by ROM code using the
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* Configuration Header feature
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* Please have a look at the respective functions to see what gets
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* done in each of these cases
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* This function is called with SRAM stack.
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*/
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void s_init(void)
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{
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init_omap_revision();
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hw_data_init();
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#ifdef CONFIG_SPL_BUILD
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if (warm_reset() &&
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(is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
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force_emif_self_refresh();
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#endif
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watchdog_init();
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set_mux_conf_regs();
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#ifdef CONFIG_SPL_BUILD
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srcomp_enable();
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setup_clocks_for_console();
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do_io_settings();
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#endif
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prcm_init();
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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board_early_init_f();
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#endif
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/* For regular u-boot sdram_init() is called from dram_init() */
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sdram_init();
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}
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#endif
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/*
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* Routine: wait_for_command_complete
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* Description: Wait for posting to finish on watchdog
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*/
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void wait_for_command_complete(struct watchdog *wd_base)
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{
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int pending = 1;
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do {
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pending = readl(&wd_base->wwps);
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} while (pending);
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}
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/*
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* Routine: watchdog_init
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* Description: Shut down watch dogs
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*/
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void watchdog_init(void)
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{
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struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
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writel(WD_UNLOCK1, &wd2_base->wspr);
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wait_for_command_complete(wd2_base);
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writel(WD_UNLOCK2, &wd2_base->wspr);
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}
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/*
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* This function finds the SDRAM size available in the system
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* based on DMM section configurations
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* This is needed because the size of memory installed may be
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* different on different versions of the board
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*/
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u32 omap_sdram_size(void)
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{
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u32 section, i, valid;
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u64 sdram_start = 0, sdram_end = 0, addr,
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size, total_size = 0, trap_size = 0, trap_start = 0;
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for (i = 0; i < 4; i++) {
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section = __raw_readl(DMM_BASE + i*4);
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valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
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(EMIF_SDRC_ADDRSPC_SHIFT);
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addr = section & EMIF_SYS_ADDR_MASK;
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/* See if the address is valid */
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if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
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(addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
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size = ((section & EMIF_SYS_SIZE_MASK) >>
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EMIF_SYS_SIZE_SHIFT);
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size = 1 << size;
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size *= SZ_16M;
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if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
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if (!sdram_start || (addr < sdram_start))
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sdram_start = addr;
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if (!sdram_end || ((addr + size) > sdram_end))
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sdram_end = addr + size;
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} else {
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trap_size = size;
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trap_start = addr;
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}
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}
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}
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if ((trap_start >= sdram_start) && (trap_start < sdram_end))
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total_size = (sdram_end - sdram_start) - (trap_size);
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else
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total_size = sdram_end - sdram_start;
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return total_size;
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}
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/*
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* Routine: dram_init
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* Description: sets uboots idea of sdram size
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*/
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int dram_init(void)
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{
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sdram_init();
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gd->ram_size = omap_sdram_size();
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return 0;
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}
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/*
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* Print board information
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*/
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int checkboard(void)
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{
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puts(sysinfo.board_string);
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return 0;
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}
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/*
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* get_device_type(): tell if GP/HS/EMU/TST
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*/
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u32 get_device_type(void)
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{
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return (readl((*ctrl)->control_status) &
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(DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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/*
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* Print CPU information
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*/
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int print_cpuinfo(void)
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{
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puts("CPU : ");
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omap_rev_string();
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return 0;
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}
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#endif
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