Dinh Nguyen c624d07f3f arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines ... The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>		2015-11-03 17:32:16 +01:00
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include/mach	arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines	2015-11-03 17:32:16 +01:00
clock_manager.c	arm: socfpga: Fix delay in clock manager	2015-08-23 11:56:19 +02:00
fpga_manager.c	ARM: socfpga: move SoC sources to mach-socfpga	2015-05-07 05:21:12 +02:00
freeze_controller.c	arm: socfpga: Fix delay in freeze controller	2015-08-23 11:56:19 +02:00
Kconfig	arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files	2015-09-23 03:55:28 +02:00
Makefile	arm: socfpga: Move wrappers into platform directory	2015-08-23 11:56:19 +02:00
misc.c	arm: socfpga: enable data/inst prefetch and shared override in the L2	2015-10-17 01:47:31 +02:00
qts-filter.sh	arm: socfpga: Make the pinmux table const u8	2015-08-23 11:56:20 +02:00
reset_manager.c	arm: socfpga: Assure ISWGRP 0 and 1 are inited	2015-09-04 11:54:20 +02:00
scan_manager.c	arm: socfpga: scan: Add code to get FPGA ID	2015-08-08 14:14:30 +02:00
spl.c	arm: socfpga: Do not call board_init_r() from board_init_f()	2015-09-04 11:54:20 +02:00
system_manager.c	arm: socfpga: Make the pinmux table const u8	2015-08-23 11:56:20 +02:00
timer.c	ARM: socfpga: move SoC sources to mach-socfpga	2015-05-07 05:21:12 +02:00
wrap_iocsr_config.c	arm: socfpga: Switch to filtered QTS files	2015-08-23 11:56:20 +02:00
wrap_pinmux_config.c	arm: socfpga: Make the pinmux table const u8	2015-08-23 11:56:20 +02:00
wrap_pll_config.c	arm: socfpga: Move wrappers into platform directory	2015-08-23 11:56:19 +02:00
wrap_sdram_config.c	arm: socfpga: Switch to filtered QTS files	2015-08-23 11:56:20 +02:00