Vladimir Zapolskiy 4c90234586 lpc32xx: fix calculation of HCLK PLL output clock ... Execution branches on feedback mode are swapped, this has no effect if default direct mode is on (then p_div is equal to 1 and Fout equals to Fcco), that's why the problem remained unnoticed for a long time. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>		2015-10-11 17:12:13 -04:00
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clk.c	lpc32xx: fix calculation of HCLK PLL output clock	2015-10-11 17:12:13 -04:00
cpu.c	lpc32xx: cpu: add support for soft reset	2015-08-17 08:10:58 -04:00
devices.c	lpc32xx: remove duplicated DMA_CLK_ENABLE bit definition	2015-09-11 14:05:35 -04:00
dram.c	lpc32xx: add support for board work_92105	2015-04-10 14:23:39 +02:00
lowlevel_init.S	lpc32xx: add support for board work_92105	2015-04-10 14:23:39 +02:00
Makefile	lpc32xx: add support for board work_92105	2015-04-10 14:23:39 +02:00
timer.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00