mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 23:02:59 +00:00
ed2f65f010
Add board code for the R8A77980 V3HSK board. Add CPLD sysreset driver to the R-Car V3H SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync configs and board code with V3H Condor, squash CPLD driver in]
28 lines
643 B
C
28 lines
643 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* include/configs/v3hsk.h
|
|
* This file is V3HSK board configuration.
|
|
*
|
|
* Copyright (C) 2019 Renesas Electronics Corporation
|
|
* Copyright (C) 2019 Cogent Embedded, Inc.
|
|
*/
|
|
|
|
#ifndef __V3HSK_H
|
|
#define __V3HSK_H
|
|
|
|
#include "rcar-gen3-common.h"
|
|
|
|
/* Environment compatibility */
|
|
|
|
/* SH Ether */
|
|
#define CFG_SH_ETHER_USE_PORT 0
|
|
#define CFG_SH_ETHER_PHY_ADDR 0x0
|
|
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
|
|
#define CFG_SH_ETHER_CACHE_WRITEBACK
|
|
#define CFG_SH_ETHER_CACHE_INVALIDATE
|
|
#define CFG_SH_ETHER_ALIGNE_SIZE 64
|
|
|
|
/* Board Clock */
|
|
/* XTAL_CLK : 33.33MHz */
|
|
|
|
#endif /* __V3HSK_H */
|