u-boot/arch/riscv
Heinrich Schuchardt d14222e7c1 risc-v: implement DBCN write byte
The DBCN extension provides a Console Write Byte call.
Implement function sbi_dbcn_write_byte to invoke it.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:55 +08:00
..
cpu riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT 2023-09-05 10:53:46 +08:00
dts riscv: jh7110: enable riscv,timer in the device tree 2023-09-05 10:53:36 +08:00
include/asm risc-v: implement DBCN write byte 2023-09-05 10:53:55 +08:00
lib risc-v: implement DBCN write byte 2023-09-05 10:53:55 +08:00
config.mk riscv: Support CONFIG_REMAKE_ELF 2023-04-20 20:45:08 +08:00
Kconfig riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE 2023-08-10 10:58:12 +08:00
Makefile riscv: support building double-float modules 2022-10-20 15:22:21 +08:00