mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
308520b8f2
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
149 lines
4.1 KiB
C
149 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright 2017-2018 NXP
|
|
*/
|
|
|
|
#ifndef __LS1088_COMMON_H
|
|
#define __LS1088_COMMON_H
|
|
|
|
/* SPL build */
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#define SPL_NO_BOARDINFO
|
|
#define SPL_NO_QIXIS
|
|
#define SPL_NO_PCI
|
|
#define SPL_NO_ENV
|
|
#define SPL_NO_RTC
|
|
#define SPL_NO_USB
|
|
#define SPL_NO_SATA
|
|
#define SPL_NO_QSPI
|
|
#define SPL_NO_IFC
|
|
#endif
|
|
|
|
#include <asm/arch/stream_id_lsch3.h>
|
|
#include <asm/arch/config.h>
|
|
#include <asm/arch/soc.h>
|
|
|
|
#define LS1088ARDB_PB_BOARD 0x4A
|
|
/* Link Definitions */
|
|
|
|
/* Link Definitions */
|
|
#define CFG_SYS_FSL_QSPI_BASE 0x20000000
|
|
|
|
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
|
|
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
|
|
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
|
|
#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
|
|
/*
|
|
* SMP Definitinos
|
|
*/
|
|
#define CPU_RELEASE_ADDR secondary_boot_addr
|
|
|
|
/* GPIO */
|
|
|
|
/* I2C */
|
|
|
|
|
|
/* Serial Port */
|
|
#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
|
|
|
|
/*
|
|
* During booting, IFC is mapped at the region of 0x30000000.
|
|
* But this region is limited to 256MB. To accommodate NOR, promjet
|
|
* and FPGA. This region is divided as below:
|
|
* 0x30000000 - 0x37ffffff : 128MB : NOR flash
|
|
* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
|
|
* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
|
|
*
|
|
* To accommodate bigger NOR flash and other devices, we will map IFC
|
|
* chip selects to as below:
|
|
* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
|
|
* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
|
|
* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
|
|
* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
|
|
* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
|
|
*
|
|
* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
|
|
* CFG_SYS_FLASH_BASE has the final address (core view)
|
|
* CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
|
|
* CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
|
|
* CONFIG_TEXT_BASE is linked to 0x30000000 for booting
|
|
*/
|
|
|
|
#define CFG_SYS_FLASH_BASE 0x580000000ULL
|
|
#define CFG_SYS_FLASH_BASE_PHYS 0x80000000
|
|
#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
|
|
|
|
#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000
|
|
#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
|
|
|
|
#ifndef __ASSEMBLY__
|
|
unsigned long long get_qixis_addr(void);
|
|
#endif
|
|
|
|
#define QIXIS_BASE get_qixis_addr()
|
|
#define QIXIS_BASE_PHYS 0x20000000
|
|
#define QIXIS_BASE_PHYS_EARLY 0xC000000
|
|
|
|
|
|
#define CFG_SYS_NAND_BASE 0x530000000ULL
|
|
#define CFG_SYS_NAND_BASE_PHYS 0x30000000
|
|
|
|
|
|
/* MC firmware */
|
|
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
|
|
#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
|
|
#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
|
|
#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
|
|
#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
|
|
#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
|
|
#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
|
|
|
|
/*
|
|
* Carve out a DDR region which will not be used by u-boot/Linux
|
|
*
|
|
* It will be used by MC and Debug Server. The MC region must be
|
|
* 512MB aligned, so the min size to hide is 512MB.
|
|
*/
|
|
|
|
#if defined(CONFIG_FSL_MC_ENET)
|
|
#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
|
|
#endif
|
|
|
|
/* Miscellaneous configurable options */
|
|
|
|
/* Physical Memory Map */
|
|
|
|
#define HWCONFIG_BUFFER_SIZE 128
|
|
|
|
#ifndef SPL_NO_ENV
|
|
/* Initial environment variables */
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
|
"loadaddr=0x80100000\0" \
|
|
"kernel_addr=0x100000\0" \
|
|
"ramdisk_addr=0x800000\0" \
|
|
"ramdisk_size=0x2000000\0" \
|
|
"fdt_high=0xa0000000\0" \
|
|
"initrd_high=0xffffffffffffffff\0" \
|
|
"kernel_start=0x581000000\0" \
|
|
"kernel_load=0xa0000000\0" \
|
|
"kernel_size=0x2800000\0" \
|
|
"console=ttyAMA0,38400n8\0" \
|
|
"mcinitcmd=fsl_mc start mc 0x580a00000" \
|
|
" 0x580e00000 \0"
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPL
|
|
#ifdef CONFIG_NXP_ESBC
|
|
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
|
/*
|
|
* HDR would be appended at end of image and copied to DDR along
|
|
* with U-Boot image. Here u-boot max. size is 512K. So if binary
|
|
* size increases then increase this size in case of secure boot as
|
|
* it uses raw u-boot image instead of fit image.
|
|
*/
|
|
#endif /* ifdef CONFIG_NXP_ESBC */
|
|
|
|
#endif
|
|
|
|
#endif /* __LS1088_COMMON_H */
|