mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
308520b8f2
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
305 lines
9.8 KiB
C
305 lines
9.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#ifndef __LS1043AQDS_H__
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#define __LS1043AQDS_H__
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#include "ls1043a_common.h"
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/* Physical Memory Map */
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#define SPD_EEPROM_ADDRESS 0x51
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define RGMII_PHY1_ADDR 0x1
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#define RGMII_PHY2_ADDR 0x2
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#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
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#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
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#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
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#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
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/* PHY address on QSGMII riser card on slot 1 */
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#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
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#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
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#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
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#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
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/* PHY address on QSGMII riser card on slot 2 */
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#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
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#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
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#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
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#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
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#endif
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/*
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* IFC Definitions
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*/
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CFG_SYS_NOR0_CSPR_EXT (0x0)
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#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CFG_SYS_NOR1_CSPR_EXT (0x0)
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#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
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+ 0x8000000) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
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#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_TRHZ_80)
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#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1a) | \
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0xe) | \
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FTIM2_NOR_TWP(0x1c))
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#define CFG_SYS_NOR_FTIM3 0
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#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
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CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
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#define CFG_SYS_WRITE_SWAPPED_DATA
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/*
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* NAND Flash Definitions
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*/
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#define CFG_SYS_NAND_BASE 0x7e800000
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#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
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#define CFG_SYS_NAND_CSPR_EXT (0x0)
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#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x7) | \
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FTIM0_NAND_TWH(0xa))
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#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0xe) | \
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FTIM1_NAND_TRP(0x18))
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#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
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FTIM2_NAND_TREH(0xa) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CFG_SYS_NAND_FTIM3 0x0
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#endif
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#ifdef CONFIG_NAND_BOOT
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#define CFG_SYS_NAND_U_BOOT_SIZE (640 << 10)
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#endif
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#if defined(CONFIG_TFABOOT) || \
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defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#endif
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/*
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* QIXIS Definitions
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*/
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#ifdef CONFIG_FSL_QIXIS
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#define QIXIS_BASE 0x7fb00000
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#define QIXIS_BASE_PHYS QIXIS_BASE
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#define CFG_SYS_I2C_FPGA_ADDR 0x66
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#define QIXIS_LBMAP_SWITCH 6
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x04
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#define QIXIS_LBMAP_NAND 0x09
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#define QIXIS_LBMAP_SD 0x00
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#define QIXIS_LBMAP_SD_QSPI 0xff
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#define QIXIS_LBMAP_QSPI 0xff
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#define QIXIS_RCW_SRC_NAND 0x106
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#define QIXIS_RCW_SRC_SD 0x040
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#define QIXIS_RCW_SRC_QSPI 0x045
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#define QIXIS_RST_CTL_RESET 0x41
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define CFG_SYS_FPGA_CSPR_EXT (0x0)
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#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
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#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_NOR_MODE_AVD_NOR | \
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CSOR_NOR_TRHZ_80)
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/*
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* QIXIS Timing parameters for IFC GPCM
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*/
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#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
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FTIM0_GPCM_TEADC(0x20) | \
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FTIM0_GPCM_TEAHC(0x10))
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#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
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FTIM1_GPCM_TRAD(0x1f))
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#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
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FTIM2_GPCM_TCH(0x8) | \
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FTIM2_GPCM_TWP(0xf0))
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#define CFG_SYS_FPGA_FTIM3 0x0
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#endif
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#ifdef CONFIG_TFABOOT
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
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#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
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#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
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#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
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#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
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#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
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#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
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#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
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#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
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#else
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#ifdef CONFIG_NAND_BOOT
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
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#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
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#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
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#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
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#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
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#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
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#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
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#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
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#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
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#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
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#else
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
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#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
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#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
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#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
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#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
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#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
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#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
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#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
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#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
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#endif
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#endif
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/*
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* I2C bus multiplexer
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*/
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#define I2C_MUX_PCA_ADDR_PRI 0x77
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#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
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#define I2C_RETIMER_ADDR 0x18
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#define I2C_MUX_CH_DEFAULT 0x8
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#define I2C_MUX_CH_CH7301 0xC
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#define I2C_MUX_CH5 0xD
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#define I2C_MUX_CH7 0xF
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#define I2C_MUX_CH_VOL_MONITOR 0xa
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/* Voltage monitor on channel 2*/
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#define I2C_VOL_MONITOR_ADDR 0x40
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#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
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#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
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#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
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/* The lowest and highest voltage allowed for LS1043AQDS */
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#define VDD_MV_MIN 819
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#define VDD_MV_MAX 1212
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/*
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* Miscellaneous configurable options
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*/
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/*
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* Environment
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*/
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#include <asm/fsl_secure_boot.h>
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#endif /* __LS1043AQDS_H__ */
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