mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
ddb56f371a
Add initial support for Advantech RSB-3720 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Signed-off-by: Darren Huang <darren.huang@advantech.com.tw> Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw> Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw> Signed-off-by: Tim Liang <tim.liang@advantech.com.tw> Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com> Cc: Peng Fan (OSS) <peng.fan@oss.nxp.com>
223 lines
6.3 KiB
C
223 lines
6.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright 2019 NXP
|
|
* Copyright 2022 Linaro
|
|
*/
|
|
|
|
#ifndef __IMX8MP_RSB3720_H
|
|
#define __IMX8MP_RSB3720_H
|
|
|
|
#include <linux/sizes.h>
|
|
#include <linux/stringify.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <config_distro_bootcmd.h>
|
|
|
|
#define CONFIG_HAS_ETH1
|
|
|
|
#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
|
|
|
|
#define CONFIG_SPL_MAX_SIZE (152 * 1024)
|
|
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
|
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
|
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
|
#define CONFIG_SPL_STACK 0x960000
|
|
#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
|
|
#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
|
|
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
|
|
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
|
|
|
|
#define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \
|
|
* GD_FLG_FULL_MALLOC_INIT \
|
|
* set \
|
|
*/
|
|
|
|
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
|
|
|
#if defined(CONFIG_NAND_BOOT)
|
|
#define CONFIG_SPL_NAND_SUPPORT
|
|
#define CONFIG_SPL_DMA
|
|
#define CONFIG_SPL_NAND_MXS
|
|
#define CONFIG_SPL_NAND_BASE
|
|
#define CONFIG_SPL_NAND_IDENT
|
|
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of \
|
|
* first 64MB boot area \
|
|
*/
|
|
|
|
/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full
|
|
* boot image (not only FIT part) to the mtdpart, so we check both two offsets
|
|
*/
|
|
#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
|
|
(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
#define CONFIG_REMAKE_ELF
|
|
/* ENET Config */
|
|
/* ENET1 */
|
|
#if defined(CONFIG_CMD_NET)
|
|
#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
|
|
|
|
#define CONFIG_FEC_XCV_TYPE RGMII
|
|
#define CONFIG_FEC_MXC_PHYADDR 4
|
|
#define FEC_QUIRK_ENET_MAC
|
|
|
|
#define DWC_NET_PHYADDR 4
|
|
#ifdef CONFIG_DWC_ETH_QOS
|
|
#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
|
|
#endif
|
|
|
|
#define PHY_ANEG_TIMEOUT 20000
|
|
|
|
#endif
|
|
|
|
#if CONFIG_IS_ENABLED(CMD_MMC)
|
|
# define BOOT_TARGET_MMC(func) \
|
|
func(MMC, mmc, 2) \
|
|
func(MMC, mmc, 1)
|
|
#else
|
|
# define BOOT_TARGET_MMC(func)
|
|
#endif
|
|
|
|
#if CONFIG_IS_ENABLED(CMD_PXE)
|
|
# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
|
|
#else
|
|
# define BOOT_TARGET_PXE(func)
|
|
#endif
|
|
|
|
#if CONFIG_IS_ENABLED(CMD_DHCP)
|
|
# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
|
|
#else
|
|
# define BOOT_TARGET_DHCP(func)
|
|
#endif
|
|
|
|
#define BOOT_TARGET_DEVICES(func) \
|
|
BOOT_TARGET_MMC(func) \
|
|
BOOT_TARGET_PXE(func) \
|
|
BOOT_TARGET_DHCP(func)
|
|
|
|
/* Initial environment variables */
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
BOOTENV \
|
|
"script=boot.scr\0" \
|
|
"image=Image\0" \
|
|
"splashimage=0x50000000\0" \
|
|
"console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \
|
|
"fdt_addr=0x43000000\0" \
|
|
"fdt_addr_r=0x43000000\0" \
|
|
"boot_fit=no\0" \
|
|
"dfu_alt_info=mmc 2=flash-bin raw 0 0x1B00 mmcpart 1\0" \
|
|
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
|
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
|
"initrd_addr=0x43800000\0" \
|
|
"bootm_size=0x10000000\0" \
|
|
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
|
"mmcpart=1\0" \
|
|
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
|
"mmcautodetect=yes\0" \
|
|
"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
|
|
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
|
"bootscript=echo Running bootscript from mmc ...; " \
|
|
"source\0" \
|
|
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
|
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
|
"kernel_addr_r=0x40480000\0" \
|
|
"pxefile_addr_r=0x40480000\0" \
|
|
"ramdisk_addr_r=0x43800000\0" \
|
|
"mmcboot=echo Booting from mmc ...; " \
|
|
"run mmcargs; " \
|
|
"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
|
|
"bootm ${loadaddr}; " \
|
|
"else " \
|
|
"if run loadfdt; then " \
|
|
"booti ${loadaddr} - ${fdt_addr}; " \
|
|
"else " \
|
|
"echo WARN: Cannot load the DT; " \
|
|
"fi; " \
|
|
"fi;\0" \
|
|
"netargs=setenv bootargs ${jh_clk} console=${console} " \
|
|
"root=/dev/nfs " \
|
|
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
|
"netboot=echo Booting from net ...; " \
|
|
"run netargs; " \
|
|
"if test ${ip_dyn} = yes; then " \
|
|
"setenv get_cmd dhcp; " \
|
|
"else " \
|
|
"setenv get_cmd tftp; " \
|
|
"fi; " \
|
|
"${get_cmd} ${loadaddr} ${image}; " \
|
|
"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
|
|
"bootm ${loadaddr}; " \
|
|
"else " \
|
|
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
|
"booti ${loadaddr} - ${fdt_addr}; " \
|
|
"else " \
|
|
"echo WARN: Cannot load the DT; " \
|
|
"fi; " \
|
|
"fi;\0"
|
|
|
|
/* Link Definitions */
|
|
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
|
#define CONFIG_SYS_INIT_SP_OFFSET \
|
|
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
#define CONFIG_SYS_INIT_SP_ADDR \
|
|
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
|
|
|
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
|
|
|
/* Totally 6GB or 4G DDR */
|
|
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
|
#define PHYS_SDRAM 0x40000000
|
|
#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
|
|
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
|
|
#define PHYS_SDRAM_2 0x100000000
|
|
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
|
|
#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
|
|
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
|
|
#define PHYS_SDRAM_2 0xC0000000
|
|
#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
|
|
#endif
|
|
|
|
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
|
|
|
|
/* Monitor Command Prompt */
|
|
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
|
#define CONFIG_SYS_CBSIZE 2048
|
|
#define CONFIG_SYS_MAXARGS 64
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
|
sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
|
|
#define CONFIG_IMX_BOOTAUX
|
|
|
|
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
|
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
|
|
|
#ifdef CONFIG_FSL_FSPI
|
|
#define FSL_FSPI_FLASH_SIZE SZ_32M
|
|
#define FSL_FSPI_FLASH_NUM 1
|
|
#define FSPI0_BASE_ADDR 0x30bb0000
|
|
#define FSPI0_AMBA_BASE 0x0
|
|
#define CONFIG_FSPI_QUAD_SUPPORT
|
|
|
|
#define CONFIG_SYS_FSL_FSPI_AHB
|
|
#endif
|
|
|
|
#ifdef CONFIG_NAND_MXS
|
|
|
|
/* NAND stuff */
|
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
|
#define CONFIG_SYS_NAND_BASE 0x20000000
|
|
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
|
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
|
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
|
#endif /* CONFIG_NAND_MXS */
|
|
|
|
#define CONFIG_SYS_I2C_SPEED 100000
|
|
|
|
#endif /* __IMX8MP_RSB3720_H */
|