u-boot/arch/x86/dts
Simon Glass a9aff2f46a x86: dts: Add SPI flash MRC details for chromebook_link
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
..
include Makefile: Support include files for .dts files 2014-06-20 11:55:03 -06:00
microcode x86: Integrate Tunnel Creek processor microcode 2014-12-18 17:26:05 -07:00
.gitignore dts: generate multiple device tree blobs 2014-02-19 11:10:05 -05:00
chromebook_link.dts x86: dts: Add SPI flash MRC details for chromebook_link 2015-01-24 06:13:45 -07:00
crownbay.dts x86: crownbay: Add pci devices in the dts file 2015-01-13 07:24:57 -08:00
Makefile x86: Make chromebook_link the default board for coreboot 2015-01-13 07:25:04 -08:00
serial.dtsi x86: Use ePAPR defined properties for x86-uart 2015-01-13 07:24:57 -08:00
skeleton.dtsi x86: fdt: Create basic .dtsi file for coreboot 2012-12-06 14:30:42 -08:00