mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 05:04:26 +00:00
8ef7df5df3
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
29 lines
1.2 KiB
Makefile
29 lines
1.2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
|
|
#
|
|
# Copyright (c) 2016, NVIDIA CORPORATION.
|
|
#
|
|
|
|
obj-$(CONFIG_DM_RESET) += reset-uclass.o
|
|
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
|
|
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
|
|
obj-$(CONFIG_STI_RESET) += sti-reset.o
|
|
obj-$(CONFIG_STM32_RESET) += stm32-reset.o
|
|
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
|
|
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
|
|
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
|
|
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
|
|
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
|
|
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
|
|
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
|
|
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
|
|
obj-$(CONFIG_RESET_MESON) += reset-meson.o
|
|
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
|
|
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
|
|
obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
|
|
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
|
|
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
|
|
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
|
|
obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o
|
|
obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
|
|
obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
|
|
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
|