Tom Rini a74f0c7cb5 am33xx: Correct and clean up ddr_regs struct ... The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: Tom Rini <trini@ti.com>		2012-09-01 14:58:13 +02:00
..
clock.h	ARM:AM33XX: Add clock definitions	2011-10-27 21:56:36 +02:00
clocks_am33xx.h	omap: am33xx: accomodate input clocks other than 24 Mhz	2012-07-07 14:07:35 +02:00
common_def.h	am33xx: pin mux defintions for CPSW switch	2012-09-01 14:58:11 +02:00
cpu.h	am33xx: CPSW init and definitions	2012-09-01 14:58:11 +02:00
ddr_defs.h	am33xx: Correct and clean up ddr_regs struct	2012-09-01 14:58:13 +02:00
gpio.h	omap: am33xx: enable gpio support	2012-09-01 14:58:09 +02:00
hardware.h	am33xx: Remove DMM_BASE define	2012-09-01 14:58:11 +02:00
i2c.h	am33xx: Fix i2c sampling rate typo	2012-07-07 14:07:22 +02:00
mmc_host_def.h	ARM:OMAP+:MMC: Add parameters to MMC init	2012-05-15 08:31:22 +02:00
omap.h	ARM:AM33XX: Add SPL support for AM335X EVM	2012-01-16 08:40:12 +01:00
sys_proto.h	am33xx: Move the call to ddr_pll_config, make it take the frequency	2012-09-01 14:58:12 +02:00