Green Wan a74e9d899d riscv: cpu: fu740: Add support for cpu fu740 ... Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2021-05-31 16:35:53 +08:00
..
ax25	cpu: Rename SPL_CPU_SUPPORT to SPL_CPU	2021-03-27 15:04:31 +13:00
fu540	riscv: Split SiFive CLINT support between SPL and U-Boot proper	2021-05-17 16:42:24 +08:00
fu740	riscv: cpu: fu740: Add support for cpu fu740	2021-05-31 16:35:53 +08:00
generic	riscv: qemu: Switch to use binman to generate u-boot.itb	2021-05-19 17:01:51 +08:00
cpu.c	treewide: Convert macro and uses of __section(foo) to __section("foo")	2021-05-24 14:21:30 -04:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: cpu: Add callback to init each core	2021-05-05 16:11:22 +08:00
u-boot-spl.lds	riscv: Add _image_binary_end for SPL	2020-06-04 09:44:08 +08:00
u-boot.lds	riscv: Fix breakage caused by linker relaxation	2020-02-10 14:50:53 +08:00