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f80d6472b4
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com> |
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.. | ||
arm_ddr_gen3.c | ||
ctrl_regs.c | ||
ddr1_dimm_params.c | ||
ddr2_dimm_params.c | ||
ddr3_dimm_params.c | ||
ddr4_dimm_params.c | ||
fsl_ddr_gen4.c | ||
interactive.c | ||
lc_common_dimm_params.c | ||
main.c | ||
Makefile | ||
mpc85xx_ddr_gen1.c | ||
mpc85xx_ddr_gen2.c | ||
mpc85xx_ddr_gen3.c | ||
mpc86xx_ddr.c | ||
options.c | ||
util.c |