u-boot/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
Marek Vasut 1587e689b3 ARM: dts: stm32: Fix and expand PLL configuration comments
Fix the frequencies listed in PLL configuration comments to match
the actual frequencies programmed into hardware. Furthermore, add
a comment which explains how those frequencies are calculated, so
it won't be necessary to look it up all over the datasheet and
make more mistakes in the calculation in the future.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-10-18 08:36:10 +02:00

223 lines
3.4 KiB
Text

// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright : STMicroelectronics 2018
*
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
/ {
u-boot,dm-pre-reloc;
aliases {
eeprom0 = &eeprom0;
};
config {
dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
};
};
&flash0 {
u-boot,dm-spl;
};
&i2c4 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
eeprom0: eeprom@53 {
};
};
&i2c4_pins_a {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
};
};
&pmic {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
regulators {
u-boot,dm-spl;
};
};
&pwr_regulators {
u-boot,dm-spl;
};
&qspi {
u-boot,dm-spl;
};
&qspi_clk_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&qspi_bk1_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
/*
* cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
* frac = < f >;
*
* PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
* DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
* m ... for PLL1,2: m=2 ; for PLL3,4: m=1
* XTAL = 24 MHz
*
* VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
* P = VCO / (P + 1)
* Q = VCO / (Q + 1)
* R = VCO / (R + 1)
*/
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 5 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};
&reg11 {
u-boot,dm-spl;
};
&reg18 {
u-boot,dm-spl;
};
&usb33 {
u-boot,dm-spl;
};
&usbotg_hs_pins_a {
u-boot,dm-spl;
};
&usbotg_hs {
u-boot,dm-spl;
};
&usbphyc {
u-boot,dm-spl;
};
&usbphyc_port0 {
u-boot,dm-spl;
};
&usbphyc_port1 {
u-boot,dm-spl;
};
&vdd_usb {
u-boot,dm-spl;
};