mirror of
https://github.com/AsahiLinux/u-boot
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a2ac2b964b
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
118 lines
3.2 KiB
C
118 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* Ilko Iliev <iliev@ronetix.at>
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* Asen Dimov <dimov@ronetix.at>
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* Ronetix GmbH <www.ronetix.at>
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*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* Configuation settings for the PM9G45 board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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/* general purpose I/O */
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE 0x70000000
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3
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#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
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#endif
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/* Ethernet */
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#define CONFIG_RESET_PHY_R
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#define CONFIG_AT91_WANTS_COMMON_PHY
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#ifdef CONFIG_NAND_BOOT
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/* bootstrap + u-boot + env in nandflash */
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#define CONFIG_BOOTCOMMAND \
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"nand read 0x70000000 0x200000 0x300000;" \
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"bootm 0x70000000"
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#elif CONFIG_SD_BOOT
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/* bootstrap + u-boot + env + linux in mmc */
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#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \
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"fatload mmc 0:1 0x72000000 zImage; " \
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"bootz 0x72000000 - 0x71000000"
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#endif
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
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128 * 1024, 0x1000)
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/* Defines for SPL */
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#define CONFIG_SPL_MAX_SIZE 0x010000
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#define CONFIG_SPL_STACK 0x310000
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SPL_BSS_START_ADDR 0x70000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
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#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#elif CONFIG_NAND_BOOT
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, }
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#endif
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#define CONFIG_SPL_ATMEL_SIZE
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#define CONFIG_SYS_MASTER_CLOCK 132096000
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#define CONFIG_SYS_AT91_PLLA 0x20c73f03
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#endif
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