mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-23 08:01:59 +00:00
a2ac2b964b
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2009-2015
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* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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* esd electronic system design gmbh <www.esd.eu>
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*
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* Configuation settings for the esd MEESC board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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/*
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* Warning: changing CONFIG_SYS_TEXT_BASE requires
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* adapting the initial boot program.
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* Since the linker has to swallow that define, we must use a pure
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* hex number here!
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*/
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
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/* Misc CPU related */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SERIAL_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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/*
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* Hardware drivers
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*/
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* SDRAM: 1 bank, min 32, max 128 MB
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* Initialized before u-boot gets started.
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*/
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#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
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#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
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/*
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* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
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* leaving the correct space for initial global data structure above
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* that address while providing maximum stack area below.
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*/
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#define CONFIG_SYS_INIT_SP_ADDR \
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(ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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# define CONFIG_SYS_MAX_NAND_DEVICE 1
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# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
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# define CONFIG_SYS_NAND_DBW_8
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# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
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# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
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#endif
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/* Ethernet */
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_RETRY_COUNT 20
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#undef CONFIG_RESET_PHY_R
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/* hw-controller addresses */
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#define CONFIG_ET1100_BASE 0x70000000
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#ifdef CONFIG_SYS_USE_DATAFLASH
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/* bootstrap + u-boot + env in dataflash on CS0 */
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#elif CONFIG_SYS_USE_NANDFLASH
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/* bootstrap + u-boot + env + linux in nandflash */
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#endif
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#define CONFIG_SYS_CBSIZE 512
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
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128*1024, 0x1000)
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#endif
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