mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-30 06:53:09 +00:00
b195134984
All flush_cache() calls in microblaze code are supposed to flush the entire instruction and data caches, so introduce flush_cache_all() helper to handle this. Also, provide implementations for flush_dcache_all() and invalidate_icache_all() so that icache and dcache u-boot commands can work. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
26 lines
677 B
C
26 lines
677 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (c) 2011 The Chromium OS Authors.
|
|
*/
|
|
|
|
#ifndef __MICROBLAZE_CACHE_H__
|
|
#define __MICROBLAZE_CACHE_H__
|
|
|
|
/*
|
|
* The microblaze can have either a 4 or 16 byte cacheline depending on whether
|
|
* you are using OPB(4) or CacheLink(16). If the board config has not specified
|
|
* a cacheline size we assume the larger value of 16 bytes for DMA buffer
|
|
* alignment.
|
|
*/
|
|
#ifdef CONFIG_SYS_CACHELINE_SIZE
|
|
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
|
#else
|
|
#define ARCH_DMA_MINALIGN 16
|
|
#endif
|
|
|
|
/**
|
|
* flush_cache_all - flush the entire instruction/data caches
|
|
*/
|
|
void flush_cache_all(void);
|
|
|
|
#endif /* __MICROBLAZE_CACHE_H__ */
|