u-boot/arch
Rajesh Bhagat a1f95ff7d7 armv8: lsch3: Add serdes and DDR voltage setup
Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-23 11:18:12 -08:00
..
arc ARC: Invalidate instruction and data caches early on boot 2018-01-19 17:59:35 +03:00
arm armv8: lsch3: Add serdes and DDR voltage setup 2018-01-23 11:18:12 -08:00
m68k m68k: Use asm-generic/io.h 2017-10-02 21:52:20 -04:00
microblaze microblaze: Use asm-generic/io.h 2017-10-02 21:52:21 -04:00
mips MIPS: Break out of cache loops for unimplemented caches 2017-11-28 21:59:30 +01:00
nds32 nds32: dts: Support ftsdc010 DM. 2017-11-30 10:04:21 +08:00
nios2 nios2: 10m50: Add CPU pre-relocation in device tree 2017-11-17 10:51:24 -05:00
powerpc drivers/misc: Share qbman init between archs 2018-01-10 12:28:47 -08:00
riscv riscv: Add Kconfig to support RISC-V 2018-01-12 08:05:12 -05:00
sandbox dm: core: parse chosen node 2018-01-15 11:35:38 -05:00
sh sh: Use asm-generic/io.h 2017-10-02 21:52:21 -04:00
x86 x86: tangier: Add Bluetooth to ACPI table 2018-01-08 16:52:25 +08:00
xtensa xtensa: Use asm-generic/io.h 2017-10-02 21:52:22 -04:00
.gitignore .gitignore: drop include/asm/proc from ignore pattern 2014-06-19 11:18:54 -04:00
Kconfig riscv: Modify generic codes to support RISC-V 2018-01-12 08:05:12 -05:00