Grzegorz Jaszczyk a007f23626 phy: marvell: fix pll initialization for second utmi port ... According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>		2021-04-29 07:45:24 +02:00
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comphy_a3700.c	phy: marvell: rename comphy related definitions to COMPHY_XX	2021-04-29 07:45:24 +02:00
comphy_a3700.h	phy: marvell: cp110: clean up driver after it was moved to atf	2021-04-29 07:45:24 +02:00
comphy_core.c	phy: marvell: cp110: remove unused definitions	2021-04-29 07:45:24 +02:00
comphy_core.h	phy: marvell: allow to initialize up to 6 USB ports	2021-04-29 07:45:24 +02:00
comphy_cp110.c	phy: marvell: fix pll initialization for second utmi port	2021-04-29 07:45:24 +02:00
comphy_mux.c	phy: marvell: cp110: clean up driver after it was moved to atf	2021-04-29 07:45:24 +02:00
Kconfig	drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3k	2016-09-27 17:29:53 +02:00
Makefile	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
sata.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
utmi_phy.h	phy: marvell: fix pll initialization for second utmi port	2021-04-29 07:45:24 +02:00