Matthew McClintock 9c6b47d53e p1014rdb: set ddr bus width properly depending on SVR ... Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>		2012-08-23 10:24:16 -05:00
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board	p1014rdb: set ddr bus width properly depending on SVR	2012-08-23 10:24:16 -05:00
nand_boot.c	nand_spl: store ecc data on the stack	2012-01-26 16:09:06 -06:00
nand_boot_fsl_elbc.c	nand/fsl_elbc: shrink SPL a bit by converting out_be32() to __raw_writel()	2012-08-22 16:07:43 -05:00
nand_boot_fsl_ifc.c	nand: Freescale Integrated Flash Controller NAND support	2011-09-29 19:01:04 -05:00
nand_boot_fsl_nfc.c	IMX: MX31: Cleanup include files and drop nasty #ifdef in drivers	2011-04-27 19:38:05 +02:00