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https://github.com/AsahiLinux/u-boot
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3f2b4d7220
Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
223 lines
4.3 KiB
Text
223 lines
4.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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/dts-v1/;
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#include "imx8ulp.dtsi"
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/ {
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model = "FSL i.MX8ULP EVK";
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compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
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chosen {
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stdout-path = &lpuart5;
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bootargs = "console=ttyLP1,115200 earlycon";
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};
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usdhc2_pwrseq: usdhc2_pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>;
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};
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};
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&lpuart5 {
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/* console */
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpuart5>;
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pinctrl-1 = <&pinctrl_lpuart5>;
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status = "okay";
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};
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&iomuxc1 {
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pinctrl_lpuart5: lpuart5grp {
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fsl,pins = <
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MX8ULP_PAD_PTF14__LPUART5_TX 0x03
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MX8ULP_PAD_PTF15__LPUART5_RX 0x03
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>;
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};
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pinctrl_lpi2c7: lpi2c7grp {
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fsl,pins = <
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MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27
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MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43
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MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
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MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
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MX8ULP_PAD_PTD10__SDHC0_D0 0x43
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MX8ULP_PAD_PTD9__SDHC0_D1 0x43
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MX8ULP_PAD_PTD8__SDHC0_D2 0x43
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MX8ULP_PAD_PTD7__SDHC0_D3 0x43
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MX8ULP_PAD_PTD6__SDHC0_D4 0x43
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MX8ULP_PAD_PTD5__SDHC0_D5 0x43
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MX8ULP_PAD_PTD4__SDHC0_D6 0x43
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MX8ULP_PAD_PTD3__SDHC0_D7 0x43
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MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
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>;
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};
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pinctrl_usdhc2_pte: usdhc2ptegrp {
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fsl,pins = <
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MX8ULP_PAD_PTE1__SDHC2_D0 0x43
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MX8ULP_PAD_PTE0__SDHC2_D1 0x43
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MX8ULP_PAD_PTE5__SDHC2_D2 0x43
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MX8ULP_PAD_PTE4__SDHC2_D3 0x43
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MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042
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MX8ULP_PAD_PTE3__SDHC2_CMD 0x43
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MX8ULP_PAD_PTE7__PTE7 0x10003
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
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MX8ULP_PAD_PTE15__ENET0_MDC 0x43
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MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
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MX8ULP_PAD_PTE17__ENET0_RXER 0x43
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MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
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MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
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MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
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MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
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MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
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MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043
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MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043
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>;
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};
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pinctrl_usbotg0_id: otg0idgrp {
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fsl,pins = <
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MX8ULP_PAD_PTF2__USB0_ID 0x10003
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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MX8ULP_PAD_PTD23__USB1_ID 0x10003
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>;
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};
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};
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&usdhc0 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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pinctrl-2 = <&pinctrl_usdhc0>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc2_pte>;
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pinctrl-1 = <&pinctrl_usdhc2_pte>;
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pinctrl-2 = <&pinctrl_usdhc2_pte>;
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pinctrl-3 = <&pinctrl_usdhc2_pte>;
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mmc-pwrseq = <&usdhc2_pwrseq>;
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max-frequency = <100000000>;
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bus-width = <4>;
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keep-power-in-suspend;
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non-removable;
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wakeup-source;
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status = "okay";
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wifi_wake_host {
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compatible = "nxp,wifi-wake-host";
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interrupt-parent = <&gpioe>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "host-wake";
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};
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};
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&lpi2c7 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c7>;
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status = "okay";
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pcal6408: gpio@21 {
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compatible = "ti,tca6408";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&flexspi0 {
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status = "okay";
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flash0: atxp032@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <66000000>;
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};
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};
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&flexspi2 {
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status = "okay";
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flash1: mt35xu512aba@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <8>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rmii";
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phy-handle = <ðphy>;
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status = "okay";
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phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@1 {
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reg = <1>;
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micrel,led-mode = <1>;
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};
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};
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};
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&usbotg0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg0_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbphy0 {
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fsl,tx-d-cal = <88>;
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbphy1 {
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fsl,tx-d-cal = <88>;
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};
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