mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
14c3261497
Add support for the Ethernut 5 open hardware design, based on Atmel's AT91SAM9XE512 SoC. V4 - Fix several coding style issues. - Move machine type to config file. - Remove use of CONFIG_ATMEL_LEGACY. Signed-off-by: Tim Schendekehl <tim.schendekehl@egnite.de>
287 lines
8.3 KiB
C
287 lines
8.3 KiB
C
/*
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* (C) Copyright 2011
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* egnite GmbH <info@egnite.de>
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*
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* Configuation settings for Ethernut 5 with AT91SAM9XE.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/hardware.h>
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/* The first stage boot loader expects u-boot running at this address. */
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#define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
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/* The first stage boot loader takes care of low level initialization. */
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* Set our official architecture number. */
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#define MACH_TYPE_ETHERNUT5 1971
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#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
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/* CPU information */
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#define CONFIG_ARM926EJS
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#define CONFIG_AT91FAMILY
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#define CONFIG_DISPLAY_CPUINFO /* Display at console. */
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#define CONFIG_ARCH_CPU_INIT
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#undef CONFIG_USE_IRQ /* Running w/o interrupts */
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/* 32kB internal SRAM */
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#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
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#define CONFIG_SRAM_SIZE (32 << 10)
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#define CONFIG_STACKSIZE (CONFIG_SRAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_STACKSIZE)
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/* 128MB SDRAM in 1 bank */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
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#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
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- CONFIG_SYS_MALLOC_LEN)
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/* 512kB on-chip NOR flash */
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# define CONFIG_SYS_MAX_FLASH_BANKS 1
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# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
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# define CONFIG_AT91_EFLASH
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# define CONFIG_SYS_MAX_FLASH_SECT 32
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# define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
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# define CONFIG_EFLASH_PROTSECTORS 1
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/* 512kB DataFlash at NPCS0 */
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#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
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#define CONFIG_HAS_DATAFLASH
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_ATMEL
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#define CONFIG_ATMEL_DATAFLASH_SPI
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
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#define DATAFLASH_TCSS (0x1a << 16)
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#define DATAFLASH_TCHS (0x1 << 24)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x3DE000
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#define CONFIG_ENV_SECT_SIZE (132 << 10)
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
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+ CONFIG_ENV_OFFSET)
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
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+ 0x042000)
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/* SPI */
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#define CONFIG_ATMEL_SPI
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#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
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#define AT91_SPI_CLK 15000000
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/* Serial port */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART3 /* USART 3 is DBGU */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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/* Misc. hardware drivers */
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#define CONFIG_AT91_GPIO
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/* Command line configuration */
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_LOADS
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_SPI
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#ifdef MINIMAL_LOADER
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#undef CONFIG_CMD_CONSOLE
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#undef CONFIG_CMD_EDITENV
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_ITEST
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_LOADB
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_SETGETDCR
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#undef CONFIG_CMD_XIMG
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#else
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_CDP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DNS
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RARP
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#define CONFIG_CMD_REISER
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_CMD_UNZIP
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#define CONFIG_CMD_USB
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#endif
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8
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#define CONFIG_NAND_ATMEL
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
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#endif
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/* JFFS2 */
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#ifdef CONFIG_CMD_JFFS2
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#define CONFIG_MTD_NAND_ECC_JFFS2
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#define CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_NAND
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#endif
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/* Ethernet */
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#define CONFIG_NET_MULTI
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_PHY_ID 0
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#define CONFIG_MACB_SEARCH_PHY
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/* MMC */
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
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#endif
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/* USB */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_STORAGE
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#endif
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/* RTC */
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#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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#endif
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/* I2C */
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#define CONFIG_SYS_MAX_I2C_BUS 1
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#define CONFIG_SYS_I2C_SLAVE 0
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SOFT_I2C
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#define I2C_SOFT_DECLARATIONS
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#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
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#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
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#define I2C_INIT { \
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at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
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at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
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at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
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at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
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at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
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}
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#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
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#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
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#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
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#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
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#define I2C_DELAY udelay(100)
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#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
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/* DHCP/BOOTP options */
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#ifdef CONFIG_CMD_DHCP
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_SYS_AUTOLOAD "n"
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#endif
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/* File systems */
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
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#define MTDIDS_DEFAULT "nand0=atmel_nand"
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#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
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#endif
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#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
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defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
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#define CONFIG_DOS_PARTITION
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#endif
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#define CONFIG_LZO
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#define CONFIG_RBTREE
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/* Boot command */
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
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"root=/dev/mtdblock0 " \
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MTDPARTS_DEFAULT \
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" rw rootfstype=jffs2"
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#endif
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/* Misc. u-boot settings */
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
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+ sizeof(CONFIG_SYS_PROMPT))
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#endif
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