mirror of
https://github.com/AsahiLinux/u-boot
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2440b5bb52
This converts the following to Kconfig: CONFIG_HSMMC2_8BIT Signed-off-by: Tom Rini <trini@konsulko.com>
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013
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* Texas Instruments Incorporated.
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* Lokesh Vutla <lokeshvutla@ti.com>
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*
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* Configuration settings for the TI DRA7XX board.
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* See ti_omap5_common.h for omap5 common settings.
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*/
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#ifndef __CONFIG_DRA7XX_EVM_H
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#define __CONFIG_DRA7XX_EVM_H
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#include <environment/ti/dfu.h>
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_MAX_MEM_MAPPED 0x80000000
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#ifndef CONFIG_QSPI_BOOT
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/* MMC ENV related defines */
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#endif
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#if (CONFIG_CONS_INDEX == 1)
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#define CONSOLEDEV "ttyS0"
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#elif (CONFIG_CONS_INDEX == 3)
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#define CONSOLEDEV "ttyS2"
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#endif
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#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
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#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
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#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
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#ifndef CONFIG_SPL_BUILD
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#define DFUARGS \
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"dfu_bufsiz=0x10000\0" \
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DFU_ALT_INFO_MMC \
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DFU_ALT_INFO_EMMC \
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DFU_ALT_INFO_RAM \
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DFU_ALT_INFO_QSPI
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#endif
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_DFU
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#define DFUARGS \
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"dfu_bufsiz=0x10000\0" \
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DFU_ALT_INFO_RAM
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#endif
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#endif
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#include <configs/ti_omap5_common.h>
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/*
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* Default to using SPI for environment, etc.
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* 0x000000 - 0x040000 : QSPI.SPL (256KiB)
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* 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
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* 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
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* 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
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* 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
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* 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
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* 0x9E0000 - 0x2000000 : USERLAND
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*/
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#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000
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#define CFG_SYS_SPI_ARGS_OFFS 0x140000
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#define CFG_SYS_SPI_ARGS_SIZE 0x80000
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/* SPI SPL */
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/* NAND support */
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#ifdef CONFIG_MTD_RAW_NAND
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/* NAND: device related configs */
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/* NAND: driver related configs */
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#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13, 14, 15, 16, 17, \
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18, 19, 20, 21, 22, 23, 24, 25, \
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26, 27, 28, 29, 30, 31, 32, 33, \
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34, 35, 36, 37, 38, 39, 40, 41, \
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42, 43, 44, 45, 46, 47, 48, 49, \
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50, 51, 52, 53, 54, 55, 56, 57, }
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#define CFG_SYS_NAND_ECCSIZE 512
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#define CFG_SYS_NAND_ECCBYTES 14
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#endif /* !CONFIG_MTD_RAW_NAND */
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/* Parallel NOR Support */
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#if defined(CONFIG_NOR)
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/* NOR: device related configs */
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#define CFG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
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#define CFG_SYS_FLASH_BASE (0x08000000)
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/* Reduce SPL size by removing unlikey targets */
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#endif /* NOR support */
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#endif /* __CONFIG_DRA7XX_EVM_H */
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