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https://github.com/AsahiLinux/u-boot
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Convert CONFIG_HSMMC2_8BIT to Kconfig
This converts the following to Kconfig: CONFIG_HSMMC2_8BIT Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
5125e136a9
commit
2440b5bb52
18 changed files with 17 additions and 13 deletions
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@ -72,6 +72,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_SLAVE=0x1
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CONFIG_SYS_I2C_SPEED=400000
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_SMSC=y
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CONFIG_MII=y
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@ -70,6 +70,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_SLAVE=0x1
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CONFIG_SYS_I2C_SPEED=400000
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_SMSC=y
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CONFIG_MII=y
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@ -73,6 +73,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_SLAVE=0x1
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CONFIG_SYS_I2C_SPEED=400000
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_SMSC=y
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CONFIG_MII=y
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@ -72,6 +72,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_SLAVE=0x1
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CONFIG_SYS_I2C_SPEED=400000
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_SMSC=y
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CONFIG_MII=y
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@ -92,6 +92,7 @@ CONFIG_MISC=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x50
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=76800000
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@ -89,6 +89,7 @@ CONFIG_MISC=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x50
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=76800000
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@ -88,6 +88,7 @@ CONFIG_MISC=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x50
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=76800000
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@ -76,6 +76,7 @@ CONFIG_SYS_RX_ETH_BUFFER=64
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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@ -101,6 +101,7 @@ CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_SPL_MMC_HS200_SUPPORT=y
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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@ -96,6 +96,7 @@ CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_SPL_MMC_HS200_SUPPORT=y
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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@ -92,6 +92,7 @@ CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_SPL_MMC_HS200_SUPPORT=y
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=76800000
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@ -52,6 +52,7 @@ CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_MMC_OMAP_HS=y
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CONFIG_HSMMC2_8BIT=y
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CONFIG_PALMAS_POWER=y
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CONFIG_SCSI=y
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CONFIG_SCSI_AHCI_PLAT=y
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@ -385,6 +385,11 @@ config MMC_OMAP36XX_PINS
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If unsure, say N.
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config HSMMC2_8BIT
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bool "Enable 8-bit interface for eMMC (interface #2)"
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depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \
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AM43XX || ARCH_KEYSTONE)
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config SH_SDHI
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bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
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depends on ARCH_RMOBILE
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@ -20,8 +20,6 @@
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#define V_OSCK 24000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK)
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#define CONFIG_HSMMC2_8BIT
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x80200000\0" \
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@ -35,9 +35,6 @@
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#include <configs/ti_omap5_common.h>
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/* Enhance our eMMC support / experience. */
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#define CONFIG_HSMMC2_8BIT
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/* CPSW Ethernet */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
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@ -36,8 +36,6 @@
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* we don't need to do it twice.
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*/
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#define CONFIG_HSMMC2_8BIT
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#include <configs/ti_armv7_omap.h>
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#define V_OSCK 24000000 /* Clock output from T2 */
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@ -48,9 +48,6 @@
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#include <configs/ti_omap5_common.h>
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/* Enhance our eMMC support / experience. */
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#define CONFIG_HSMMC2_8BIT
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/*
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* Default to using SPI for environment, etc.
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* 0x000000 - 0x040000 : QSPI.SPL (256KiB)
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@ -32,9 +32,6 @@
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/* MMC ENV related defines */
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/* Enhance our eMMC support / experience. */
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#define CONFIG_HSMMC2_8BIT
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/* Required support for the TCA642X GPIO we have on the uEVM */
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#define CFG_SYS_I2C_TCA642X_BUS_NUM 4
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#define CFG_SYS_I2C_TCA642X_ADDR 0x22
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