mirror of
https://github.com/AsahiLinux/u-boot
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aff2523f69
Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>
178 lines
4.3 KiB
ArmAsm
178 lines
4.3 KiB
ArmAsm
/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/mtrr.h>
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#include <asm/post.h>
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#include <asm/processor-flags.h>
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#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
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#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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/* Cache 4GB - MRC_SIZE_KB for MRC */
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#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
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#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
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#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
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#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
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#define NOEVICTMOD_MSR 0x2e0
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/*
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* Note: ebp must not be touched in this code as it holds the BIST
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* value (built-in self test). We preserve this value until it can
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* be written to global_data when CAR is ready for use.
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*/
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.globl car_init
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car_init:
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post_code(POST_CAR_START)
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/* Send INIT IPI to all excluding ourself */
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movl $0x000C4500, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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post_code(POST_CAR_SIPI)
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/* Zero out all fixed range and variable range MTRRs */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) / 2), %edi
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xorl %eax, %eax
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xorl %edx, %edx
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clear_mtrrs:
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movw (%esi), %bx
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movzx %bx, %ecx
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wrmsr
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add $2, %esi
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dec %edi
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jnz clear_mtrrs
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post_code(POST_CAR_MTRR)
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/* Configure the default memory type to uncacheable */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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andl $(~0x00000cff), %eax
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wrmsr
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post_code(POST_CAR_UNCACHEABLE)
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/* Set Cache-as-RAM base address */
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movl $(MTRR_PHYS_BASE_MSR(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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post_code(POST_CAR_BASE_ADDRESS)
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/* Set Cache-as-RAM mask */
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movl $(MTRR_PHYS_MASK_MSR(0)), %ecx
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $CPU_PHYSMASK_HI, %edx
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wrmsr
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post_code(POST_CAR_MASK)
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/* Enable MTRR */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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/* Enable cache (CR0.CD = 0, CR0.NW = 0) */
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movl %cr0, %eax
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andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
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invd
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movl %eax, %cr0
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/* enable the 'no eviction' mode */
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movl $NOEVICTMOD_MSR, %ecx
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rdmsr
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orl $1, %eax
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andl $~2, %eax
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wrmsr
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/* Clear the cache memory region. This will also fill up the cache */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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movl $(CACHE_AS_RAM_SIZE / 4), %ecx
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xorl %eax, %eax
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rep stosl
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/* enable the 'no eviction run' state */
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movl $NOEVICTMOD_MSR, %ecx
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rdmsr
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orl $3, %eax
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wrmsr
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post_code(POST_CAR_FILL)
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/* Enable Cache-as-RAM mode by disabling cache */
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movl %cr0, %eax
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orl $X86_CR0_CD, %eax
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movl %eax, %cr0
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRR_PHYS_BASE_MSR(1), %ecx
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xorl %edx, %edx
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movl $car_init_ret, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK_MSR(1), %ecx
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movl $CPU_PHYSMASK_HI, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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post_code(POST_CAR_ROM_CACHE)
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#ifdef CONFIG_CACHE_MRC_BIN
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/* Enable caching for ram init code to run faster */
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movl $MTRR_PHYS_BASE_MSR(2), %ecx
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movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
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xorl %edx, %edx
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wrmsr
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movl $MTRR_PHYS_MASK_MSR(2), %ecx
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movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
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movl $CPU_PHYSMASK_HI, %edx
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wrmsr
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#endif
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post_code(POST_CAR_MRC_CACHE)
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/* Enable cache */
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movl %cr0, %eax
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andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
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movl %eax, %cr0
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post_code(POST_CAR_CPU_CACHE)
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/* All CPUs need to be in Wait for SIPI state */
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wait_for_sipi:
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movl (%esi), %eax
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bt $12, %eax
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jc wait_for_sipi
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/* return */
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jmp car_init_ret
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mtrr_table:
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/* Fixed MTRRs */
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.word 0x250, 0x258, 0x259
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.word 0x268, 0x269, 0x26A
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.word 0x26B, 0x26C, 0x26D
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.word 0x26E, 0x26F
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/* Variable MTRRs */
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.word 0x200, 0x201, 0x202, 0x203
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.word 0x204, 0x205, 0x206, 0x207
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.word 0x208, 0x209, 0x20A, 0x20B
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.word 0x20C, 0x20D, 0x20E, 0x20F
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.word 0x210, 0x211, 0x212, 0x213
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mtrr_table_end:
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