u-boot/arch/arm/mach-socfpga
Marek Vasut 97a72bc286 ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5
On Gen5, when the FPGA is loaded and there was some prior interaction
between the HPS and the FPGA via bridges (e.g. Linux was running and
using some of the IPs in the FPGA) followed by warm reset, it has been
observed that there might be outstanding unfinished transactions. This
leads to an obscure misbehavior of the bridge.

When the bridge is enabled again in U-Boot and there are outstanding
transactions, a read from within the bridge address range would return
a result of the previous read instead. Example:
=> bridge enable ; md 0xff200000 1
ff200000: 1234abcd
=> bridge enable ; md 0xff200010 1
ff200010: 5678dcba <------- this is in fact a value which is stored in
                            a memory at 0xff200000
=> bridge enable ; md 0xff200000 1
ff200000: 90effe09 <------- this is in fact a value which is stored in
                            a memory at 0xff200010
and so it continues. Issuing a write does lock the system up completely.

This patch opens the FPGA bridges in 'bridge enable' command, the tears
them down again, and then opens them again. This allows these outstanding
transactions to complete and makes this misbehavior go away.

However, it is not entirely clear whether this is the correct solution.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
..
include/mach socfpga: fix include guard in misc.h (arch vs. global) 2019-11-20 22:32:00 +01:00
board.c ARM: socfpga: Reorder Arria10 SPL 2018-08-24 12:05:20 +02:00
clock_manager.c ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only 2018-08-13 22:35:42 +02:00
clock_manager_arria10.c ARM: socfpga: Reorder Arria10 SPL 2018-08-24 12:05:20 +02:00
clock_manager_gen5.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
clock_manager_s10.c arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC 2018-05-18 10:30:47 +02:00
fpga_manager.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
freeze_controller.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
Kconfig arm: socfpga: gen5: fix ERR_PTR_OFFSET 2019-11-07 18:01:13 -05:00
mailbox_s10.c arm: socfpga: mailbox: Fix off-by-one error on command length checking 2019-04-25 00:00:49 +02:00
Makefile sysreset: add support for socfpga sysreset 2019-07-21 12:45:10 +02:00
misc.c ARM: socfpga: Pull PL310 clearing into common code 2019-05-24 00:01:08 +02:00
misc_arria10.c ARM: socfpga: Add support for selecting bridges in bridge command 2019-04-29 10:08:56 +02:00
misc_gen5.c ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5 2019-11-25 13:12:56 +01:00
misc_s10.c env: Move env_set() to env.h 2019-08-11 16:43:41 -04:00
mmu-arm64_s10.c arm: socfpga: stratix10: Add MMU support for Stratix10 SoC 2018-07-12 09:22:11 +02:00
pinmux_arria10.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
qts-filter.sh SPDX: Convert a few files that were missed before 2018-05-10 20:38:35 -04:00
reset_manager_arria10.c ARM: socfpga: Zap unused reset code 2018-08-13 22:35:42 +02:00
reset_manager_gen5.c arm: socfpga: remove re-added ad-hoc reset code 2019-05-14 19:52:38 +02:00
reset_manager_s10.c arm: sofcpga: s10: remove unused ad-hoc reset code 2019-05-14 19:52:39 +02:00
scan_manager.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
spl_a10.c ARM: socfpga: Clear PL310 early in SPL 2019-05-24 00:01:08 +02:00
spl_gen5.c arm: socfpga: gen5: don't zero bss in board_init_f() 2019-08-15 08:50:02 +02:00
spl_s10.c arm: socfpga: Move Stratix 10 SDRAM driver to DM 2019-05-06 12:44:17 +02:00
system_manager_gen5.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
system_manager_s10.c arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC 2018-05-18 10:30:48 +02:00
timer.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
timer_s10.c arm: socfpga: stratix10: Add timer support for Stratix10 SoC 2018-07-12 09:22:12 +02:00
wrap_iocsr_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pinmux_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pinmux_config_s10.c arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC 2018-05-18 10:30:48 +02:00
wrap_pll_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pll_config_s10.c arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC 2018-05-18 10:30:47 +02:00
wrap_sdram_config.c arm: socfpga: make config structs const 2018-11-29 12:45:15 +01:00