mirror of
https://github.com/AsahiLinux/u-boot
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391 lines
11 KiB
C
391 lines
11 KiB
C
/*
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* Configuation settings for the Freescale MCF54455 EVB board.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef _JAMICA54455_H
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#define _JAMICA54455_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MCF5445x /* define processor family */
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#define CONFIG_M54455 /* define processor type */
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#define CONFIG_M54455EVB /* M54455EVB board */
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#undef DEBUG
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#define CONFIG_MCFUART
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#define CFG_UART_PORT (0)
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
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#undef CONFIG_WATCHDOG
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/* Command line configuration */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#undef CONFIG_CMD_LOADB
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#undef CONFIG_CMD_LOADS
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/* Network configuration */
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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# define CONFIG_NET_MULTI 1
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# define CONFIG_MII 1
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# define CONFIG_CF_DOMII
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# define CFG_DISCOVER_PHY
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# define CFG_RX_ETH_BUFFER 8
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# define CFG_FAULT_ECHO_LINK_DOWN
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# define CFG_FEC0_PINMUX 0
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# define CFG_FEC1_PINMUX 0
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# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
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# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
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# define MCFFEC_TOUT_LOOP 50000
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# define CONFIG_HAS_ETH1
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# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
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# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
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# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
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# define CONFIG_ETHPRIME "FEC0"
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# define CONFIG_IPADDR 192.162.1.2
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# define CONFIG_NETMASK 255.255.255.0
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# define CONFIG_SERVERIP 192.162.1.1
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# define CONFIG_GATEWAYIP 192.162.1.1
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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/* If CFG_DISCOVER_PHY is not defined - hardcoded */
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# ifndef CFG_DISCOVER_PHY
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# define FECDUPLEX FULL
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# define FECSPEED _100BASET
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# else
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# ifndef CFG_FAULT_ECHO_LINK_DOWN
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# define CFG_FAULT_ECHO_LINK_DOWN
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# endif
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# endif /* CFG_DISCOVER_PHY */
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#endif
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#define CONFIG_HOSTNAME M54455EVB
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
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"loadaddr=40010000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off 0 2ffff;" \
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"era 0 2ffff;" \
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"cp.b ${loadaddr} 0 ${filesize};" \
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"save\0" \
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""
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/* ATA configuration */
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#define CONFIG_ISO_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_IDE_RESET 1
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#define CONFIG_IDE_PREINIT 1
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#define CONFIG_ATAPI
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#undef CONFIG_LBA48
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#define CFG_IDE_MAXBUS 1
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#define CFG_IDE_MAXDEVICE 2
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#define CFG_ATA_BASE_ADDR 0x90000000
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#define CFG_ATA_IDE0_OFFSET 0
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#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
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#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
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#define CFG_ATA_STRIDE 4 /* Interval between registers */
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#define _IO_BASE 0
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/* Realtime clock */
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#define CONFIG_MCFRTC
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#undef RTC_DEBUG
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#define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
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/* Timer */
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#define CONFIG_MCFTMR
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#undef CONFIG_MCFPIT
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/* I2c */
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#define CONFIG_FSL_I2C
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_OFFSET 0x58000
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#define CFG_IMMR CFG_MBAR
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/* PCI */
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#define CONFIG_PCI 1
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#define CFG_PCI_MEM_BUS 0xA0000000
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#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
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#define CFG_PCI_MEM_SIZE 0x10000000
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#define CFG_PCI_IO_BUS 0xB1000000
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#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
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#define CFG_PCI_IO_SIZE 0x01000000
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#define CFG_PCI_CFG_BUS 0xB0000000
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#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
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#define CFG_PCI_CFG_SIZE 0x01000000
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/* FPGA - Spartan 2 */
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/* experiment
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#define CONFIG_FPGA CFG_SPARTAN3
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#define CONFIG_FPGA_COUNT 1
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#define CFG_FPGA_PROG_FEEDBACK
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#define CFG_FPGA_CHECK_CTRLC
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*/
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/* Input, PCI, Flexbus, and VCO */
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#define CONFIG_EXTRA_CLOCK
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#define CONFIG_PRAM 512 /* 512 KB */
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#define CFG_PROMPT "-> "
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#define CFG_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
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#define CFG_HZ 1000
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#define CFG_MBAR 0xFC000000
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR 0x80000000
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#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
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#define CFG_INIT_RAM_CTRL 0x221
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x40000000
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#define CFG_SDRAM_BASE1 0x48000000
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#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */
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#define CFG_SDRAM_CFG1 0x65311610
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#define CFG_SDRAM_CFG2 0x59670000
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#define CFG_SDRAM_CTRL 0xEA0B2000
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#define CFG_SDRAM_EMOD 0x40010000
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#define CFG_SDRAM_MODE 0x00010033
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#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
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#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
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#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
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#define CFG_BOOTPARAMS_LEN 64*1024
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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/* Initial Memory map for Linux */
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#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#define CFG_ENV_OFFSET 0x4000
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#define CFG_ENV_SECT_SIZE 0x2000
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#define CFG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OVERWRITE 1
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#undef CFG_ENV_IS_EMBEDDED
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#ifdef CFG_ATMEL_BOOT
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# define CFG_FLASH_BASE 0
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# define CFG_FLASH0_BASE CFG_CS0_BASE
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# define CFG_FLASH1_BASE CFG_CS1_BASE
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#else
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# define CFG_FLASH_BASE CFG_FLASH0_BASE
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# define CFG_FLASH0_BASE CFG_CS1_BASE
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# define CFG_FLASH1_BASE CFG_CS0_BASE
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#endif
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/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
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/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
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keep reset. */
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#undef CFG_FLASH_CFI
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#ifdef CFG_FLASH_CFI
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# define CFG_FLASH_CFI_DRIVER 1
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# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
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# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
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# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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# define CFG_FLASH_CHECKSUM
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# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
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#else
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# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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# define CFG_ATMEL_REGION 4
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# define CFG_ATMEL_TOTALSECT 11
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# define CFG_ATMEL_SECT {1, 2, 1, 7}
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# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
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# define CFG_INTEL_SECT 137
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/* max number of sectors on one chip */
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# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT)
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# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */
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# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
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# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */
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# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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# define CFG_FLASH_CHECKSUM
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#endif
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/*
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* This is setting for JFFS2 support in u-boot.
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* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
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*/
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#ifdef CFG_ATMEL_BOOT
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# define CONFIG_JFFS2_DEV "nor0"
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# define CONFIG_JFFS2_PART_SIZE 0x01000000
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# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
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#else
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# define CONFIG_JFFS2_DEV "nor0"
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# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
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# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16
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/*-----------------------------------------------------------------------
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* Memory bank definitions
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*/
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/*
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* CS0 - NOR Flash 1, 2, 4, or 8MB
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* CS1 - CompactFlash and registers
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* CS2 - CPLD
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* CS3 - FPGA
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* CS4 - Available
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* CS5 - Available
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*/
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#ifdef CFG_ATMEL_BOOT
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/* Atmel Flash */
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#define CFG_CS0_BASE 0
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#define CFG_CS0_MASK 0x00070001
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#define CFG_CS0_CTRL 0x00001140
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/* Intel Flash */
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#define CFG_CS1_BASE 0x04000000
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#define CFG_CS1_MASK 0x01FF0001
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#define CFG_CS1_CTRL 0x003F3D60
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#define CFG_ATMEL_BASE CFG_CS0_BASE
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#else
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/* Intel Flash */
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#define CFG_CS0_BASE 0
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#define CFG_CS0_MASK 0x01FF0001
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#define CFG_CS0_CTRL 0x003F3D60
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/* Atmel Flash */
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#define CFG_CS1_BASE 0x04000000
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#define CFG_CS1_MASK 0x00070001
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#define CFG_CS1_CTRL 0x00001140
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#define CFG_ATMEL_BASE CFG_CS1_BASE
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#endif
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/* CPLD */
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#define CFG_CS2_BASE 0x08000000
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#define CFG_CS2_MASK 0x00070001
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#define CFG_CS2_CTRL 0x003f1140
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/* FPGA */
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#define CFG_CS3_BASE 0x09000000
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#define CFG_CS3_MASK 0x00070001
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#define CFG_CS3_CTRL 0x00000020
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#endif /* _JAMICA54455_H */
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