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ColdFire: Add M54455EVB for MCF5445x

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Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChungLiew 2007-08-16 15:05:11 -05:00 committed by John Rigby
parent a1436a8426
commit 8ae158cd87
32 changed files with 6459 additions and 180 deletions
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2
CREDITS
View file

@ -491,7 +491,7 @@ W: www.monstr.eu
N: TsiChung Liew
E: Tsi-Chung.Liew@freescale.com
D: Support for ColdFire MCF532x
D: Support for ColdFire MCF532x, MCF5445x
W: www.freescale.com
N: Hayden Fraser

9
MAINTAINERS
View file

@ -606,6 +606,15 @@ Zachary P. Landau <zachary.landau@labxtechnologies.com>
r5200 mcf52x2
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M5329EVB mcf532x
M54455EVB mcf5445x
Hayden Fraser <Hayden.Fraser@freescale.com>
M5253EVBE mcf52x2
#########################################################################
# AVR32 Systems: #
# #

1
MAKEALL
View file

@ -624,6 +624,7 @@ LIST_coldfire=" \
M5272C3 \
M5282EVB \
M5329EVB \
M54455EVB \
r5200 \
TASREG \
"

28
Makefile
View file

@ -1692,6 +1692,34 @@ M5329BFEE_config : unconfig
fi
@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
M54455EVB_config \
M54455EVB_atmel_config \
M54455EVB_intel_config \
M54455EVB_a33_config \
M54455EVB_a66_config \
M54455EVB_i33_config \
M54455EVB_i66_config : unconfig
@case "$@" in \
M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \
M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \
M54455EVB_intel_config) FLASH=INTEL; FREQ=33333333;; \
M54455EVB_a33_config) FLASH=ATMEL; FREQ=33333333;; \
M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \
M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \
M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \
esac; \
>include/config.h ; \
if [ "$${FLASH}" == "INTEL" ] ; then \
echo "#undef CFG_ATMEL_BOOT" >> include/config.h ; \
echo "... with INTEL boot..." ; \
else \
echo "#define CFG_ATMEL_BOOT" >> include/config.h ; \
echo "... with ATMEL boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >>include/config.h ; \
echo "... with $${FREQ}Hz input clock"
@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
#########################################################################
## MPC83xx Systems
#########################################################################

1
README
View file

@ -137,6 +137,7 @@ Directory Hierarchy:
- ixp Files specific to Intel XScale IXP CPUs
- mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
- mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
- mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
- mips Files specific to MIPS CPUs
- mpc5xx Files specific to Freescale MPC5xx CPUs
- mpc5xxx Files specific to Freescale MPC5xxx CPUs

44
board/freescale/m54455evb/Makefile Normal file
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@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
board/freescale/m54455evb/config.mk Normal file
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@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0

974
board/freescale/m54455evb/flash.c Normal file
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@ -0,0 +1,974 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
#ifndef CFG_FLASH_CFI
typedef unsigned char FLASH_PORT_WIDTH;
typedef volatile unsigned char FLASH_PORT_WIDTHV;
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT
/* Intel-compatible flash commands */
#define INTEL_PROGRAM 0x00100010
#define INTEL_ERASE 0x00200020
#define INTEL_WRSETUP 0x00400040
#define INTEL_CLEAR 0x00500050
#define INTEL_LOCKBIT 0x00600060
#define INTEL_PROTECT 0x00010001
#define INTEL_STATUS 0x00700070
#define INTEL_READID 0x00900090
#define INTEL_CFIQRY 0x00980098
#define INTEL_SUSERASE 0x00B000B0
#define INTEL_PROTPROG 0x00C000C0
#define INTEL_CONFIRM 0x00D000D0
#define INTEL_WRBLK 0x00e800e8
#define INTEL_RESET 0x00FF00FF
/* Intel-compatible flash status bits */
#define INTEL_FINISHED 0x00800080
#define INTEL_OK 0x00800080
#define INTEL_ERASESUS 0x00600060
#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS)
/* 28F160C3B CFI Data offset - This could vary */
#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */
#define INTEL_CFI_PART 0x01 /* Product ID */
#define INTEL_CFI_LOCK 0x02 /* */
#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */
#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */
#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */
#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */
#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */
#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */
#define INTEL_CFI_CAP 0x28
#define INTEL_CFI_WRBUF 0x2A
#define INTEL_CFI_BANK 0x2C /* Number of Bank */
#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */
#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */
#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */
#define INTEL_CFI_SZ1B 0x30
#define INTEL_CFI_BLK2A 0x31
#define INTEL_CFI_BLK2B 0x32
#define INTEL_CFI_SZ2A 0x33
#define INTEL_CFI_SZ2B 0x34
#define FLASH_CYCLE1 0x0555
#define FLASH_CYCLE2 0x0aaa
#define WR_BLOCK 0x20
/* not in the flash.h yet */
#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */
#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */
#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */
#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */
#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
#define SYNC __asm__("nop")
/*-----------------------------------------------------------------------
* Functions
*/
ulong flash_get_size(FPWV * addr, flash_info_t * info);
int flash_get_offsets(ulong base, flash_info_t * info);
int flash_cmd_rd(volatile u16 * addr, int index);
int write_data(flash_info_t * info, ulong dest, FPW data);
int write_data_block(flash_info_t * info, ulong src, ulong dest);
int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data);
void inline spin_wheel(void);
void flash_sync_real_protect(flash_info_t * info);
uchar intel_sector_protected(flash_info_t * info, ushort sector);
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
ulong flash_init(void)
{
int i;
ulong size = 0;
ulong fbase = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
memset(&flash_info[i], 0, sizeof(flash_info_t));
switch (i) {
case 0:
fbase = (ulong) CFG_FLASH0_BASE;
break;
case 1:
fbase = (ulong) CFG_FLASH1_BASE;
break;
}
flash_get_size((FPWV *) fbase, &flash_info[i]);
flash_get_offsets((ulong) fbase, &flash_info[i]);
fbase += flash_info[i].size;
size += flash_info[i].size;
/* get the h/w and s/w protection status in sync */
flash_sync_real_protect(&flash_info[i]);
}
/* Protect monitor and environment sectors */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
return size;
}
int flash_get_offsets(ulong base, flash_info_t * info)
{
int i, j, k;
int sectors, bs, banks;
ulong start;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
int sect[] = CFG_ATMEL_SECT;
int sectsz[] = CFG_ATMEL_SECTSZ;
info->start[0] = base;
for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
for (j = 0; j < sect[i]; j++, k++) {
info->start[k + 1] = info->start[k] + sectsz[i];
info->protect[k] = 0;
}
}
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
volatile u16 *addr16 = (volatile u16 *)base;
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
*addr16 = (FPW) INTEL_READID;
banks = addr16[INTEL_CFI_BANK] & 0xff;
sectors = 0;
info->start[0] = base;
for (k = 0, i = 0; i < banks; i++) {
/* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
* To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
* Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
*/
bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
| (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
0x100);
sectors =
(addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
for (j = 0; j < sectors; j++, k++) {
info->start[k + 1] = info->start[k] + bs;
}
}
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
}
return ERR_OK;
}
void flash_print_info(flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL:
printf("INTEL ");
break;
case FLASH_MAN_ATM:
printf("ATMEL ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AT040:
printf("AT49BV040A\n");
break;
case FLASH_28F128J3A:
printf("Intel 28F128J3A\n");
break;
default:
printf("Unknown Chip Type\n");
return;
}
if (info->size > 0x100000) {
int remainder;
printf(" Size: %ld", info->size >> 20);
remainder = (info->size % 0x100000);
if (remainder) {
remainder >>= 10;
remainder = (int)((float)
(((float)remainder / (float)1024) *
10000));
printf(".%d ", remainder);
}
printf("MB in %d Sectors\n", info->sector_count);
} else
printf(" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
}
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size(FPWV * addr, flash_info_t * info)
{
volatile u16 *addr16 = (volatile u16 *)addr;
int intel = 0, banks = 0;
u16 value;
int i;
addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
switch (addr[0] & 0xff) {
case (u8) ATM_MANUFACT:
info->flash_id = FLASH_MAN_ATM;
value = addr[1];
break;
case (u8) INTEL_MANUFACT:
/* Terminate Atmel ID read */
addr[0] = (FPWV) 0x00F000F0;
/* Write auto select command: read Manufacturer ID */
/* Write auto select command sequence and test FLASH answer */
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
*addr16 = (FPW) INTEL_READID;
info->flash_id = FLASH_MAN_INTEL;
value = (addr16[INTEL_CFI_MFG] << 8);
value |= addr16[INTEL_CFI_PART] & 0xff;
intel = 1;
break;
default:
printf("Unknown Flash\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
*addr = (FPW) 0x00F000F0;
*addr = (FPW) INTEL_RESET; /* restore read mode */
return (0); /* no or unknown flash */
}
switch (value) {
case (u8) ATM_ID_LV040:
info->flash_id += FLASH_AT040;
break;
case (u16) INTEL_ID_28F128J3:
info->flash_id += FLASH_28F128J3A;
break;
case (u16) INTEL_ID_28F64P30T:
info->flash_id += FLASH_28F64P30T;
break;
case (u16) INTEL_ID_28F64P30B:
info->flash_id += FLASH_28F64P30B;
break;
case (u16) INTEL_ID_28F128P30T:
info->flash_id += FLASH_28F128P30T;
break;
case (u16) INTEL_ID_28F128P30B:
info->flash_id += FLASH_28F128P30B;
break;
case (u16) INTEL_ID_28F256P30T:
info->flash_id += FLASH_28F256P30T;
break;
case (u16) INTEL_ID_28F256P30B:
info->flash_id += FLASH_28F256P30B;
break;
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (intel) {
/* Intel spec. under CFI section */
u32 sz;
int sectors, bs;
banks = addr16[INTEL_CFI_BANK] & 0xff;
sectors = sz = 0;
for (i = 0; i < banks; i++) {
/* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
* To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
* Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
*/
bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
| (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
0x100);
sectors +=
(addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
sz += (bs * sectors);
}
info->sector_count = sectors;
info->size = sz;
*addr = (FPW) INTEL_RESET; /* restore read mode */
} else {
int sect[] = CFG_ATMEL_SECT;
int sectsz[] = CFG_ATMEL_SECTSZ;
info->sector_count = 0;
info->size = 0;
for (i = 0; i < CFG_ATMEL_REGION; i++) {
info->sector_count += sect[i];
info->size += sect[i] * sectsz[i];
}
/* reset ID mode */
addr[0] = (FPWV) 0x00F000F0;
}
if (info->sector_count > CFG_MAX_FLASH_SECT) {
printf("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count = CFG_MAX_FLASH_SECT;
}
return (info->size);
}
int flash_cmd_rd(volatile u16 * addr, int index)
{
return (int)addr[index];
}
/*
* This function gets the u-boot flash sector protection status
* (flash_info_t.protect[]) in sync with the sector protection
* status stored in hardware.
*/
void flash_sync_real_protect(flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F160C3B:
case FLASH_28F160C3T:
case FLASH_28F320C3B:
case FLASH_28F320C3T:
case FLASH_28F640C3B:
case FLASH_28F640C3T:
for (i = 0; i < info->sector_count; ++i) {
info->protect[i] = intel_sector_protected(info, i);
}
break;
default:
/* no h/w protect support */
break;
}
}
/*
* checks if "sector" in bank "info" is protected. Should work on intel
* strata flash chips 28FxxxJ3x in 8-bit mode.
* Returns 1 if sector is protected (or timed-out while trying to read
* protection status), 0 if it is not.
*/
uchar intel_sector_protected(flash_info_t * info, ushort sector)
{
FPWV *addr;
FPWV *lock_conf_addr;
ulong start;
unsigned char ret;
/*
* first, wait for the WSM to be finished. The rationale for
* waiting for the WSM to become idle for at most
* CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
* because of: (1) erase, (2) program or (3) lock bit
* configuration. So we just wait for the longest timeout of
* the (1)-(3), i.e. the erase timeout.
*/
/* wait at least 35ns (W12) before issuing Read Status Register */
/*udelay(1); */
addr = (FPWV *) info->start[sector];
*addr = (FPW) INTEL_STATUS;
start = get_timer(0);
while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
*addr = (FPW) INTEL_RESET; /* restore read mode */
printf("WSM busy too long, can't get prot status\n");
return 1;
}
}
/* issue the Read Identifier Codes command */
*addr = (FPW) INTEL_READID;
/* Intel example code uses offset of 4 for 8-bit flash */
lock_conf_addr = (FPWV *) info->start[sector];
ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0;
/* put flash back in read mode */
*addr = (FPW) INTEL_RESET;
return ret;
}
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, last;
int rcode = 0, intel = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("- missing\n");
else
printf("- no sectors to erase\n");
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
type = (info->flash_id & FLASH_VENDMASK);
printf
("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
}
if (type == FLASH_MAN_INTEL)
intel = 1;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
else
printf("\n");
start = get_timer(0);
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *) (info->start[sect]);
int min = 0;
printf(".");
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
if (intel) {
*addr = (FPW) INTEL_READID;
min = addr[INTEL_CFI_TERB] & 0xff;
min = 1 << min; /* ms */
min = (min / info->sector_count) * 1000;
/* start erase block */
*addr = (FPW) INTEL_CLEAR; /* clear status register */
*addr = (FPW) INTEL_ERASE; /* erase setup */
*addr = (FPW) INTEL_CONFIRM; /* erase confirm */
while ((*addr & (FPW) INTEL_FINISHED) !=
(FPW) INTEL_FINISHED) {
if (get_timer(start) >
CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*addr = (FPW) INTEL_SUSERASE; /* suspend erase */
*addr = (FPW) INTEL_RESET; /* reset to read mode */
rcode = 1;
break;
}
}
*addr = (FPW) INTEL_RESET; /* resest to read mode */
} else {
FPWV *base; /* first address in bank */
FPWV *atmeladdr;
flag = disable_interrupts();
atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
*atmeladdr = (u8) 0x00300030; /* erase sector */
if (flag)
enable_interrupts();
while ((*atmeladdr & (u8) 0x00800080) !=
(u8) 0x00800080) {
if (get_timer(start) >
CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
rcode = 1;
break;
}
}
*atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
} /* Atmel or Intel */
}
}
printf(" done\n");
return rcode;
}
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
if (info->flash_id == FLASH_UNKNOWN)
return 4;
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_ATM:
{
u16 data = 0;
int bytes; /* number of bytes to program in current word */
int left; /* number of bytes left to program */
int i, res;
for (left = cnt, res = 0;
left > 0 && res == 0;
addr += sizeof(data), left -=
sizeof(data) - bytes) {
bytes = addr & (sizeof(data) - 1);
addr &= ~(sizeof(data) - 1);
/* combine source and destination data so can program
* an entire word of 16 or 32 bits
*/
for (i = 0; i < sizeof(data); i++) {
data <<= 8;
if (i < bytes || i - bytes >= left)
data += *((uchar *) addr + i);
else
data += *src++;
}
data = (data >> 8) | (data << 8);
res = write_word_atm(info, (FPWV *) addr, data);
}
return res;
} /* case FLASH_MAN_ATM */
case FLASH_MAN_INTEL:
{
ulong cp, wp;
u16 data;
int count, i, l, rc, port_width;
/* get lower word aligned address */
wp = addr;
port_width = sizeof(FPW);
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < port_width; ++i, ++cp)
data = (data << 8) | (*(uchar *) cp);
if ((rc = write_data(info, wp, data)) != 0)
return (rc);
wp += port_width;
}
if (cnt > WR_BLOCK) {
/*
* handle word aligned part
*/
count = 0;
while (cnt >= WR_BLOCK) {
if ((rc =
write_data_block(info,
(ulong) src,
wp)) != 0)
return (rc);
wp += WR_BLOCK;
src += WR_BLOCK;
cnt -= WR_BLOCK;
if (count++ > 0x800) {
spin_wheel();
count = 0;
}
}
}
/* handle word aligned part */
if (cnt < WR_BLOCK) {
/*
* handle word aligned part
*/
count = 0;
while (cnt >= port_width) {
data = 0;
for (i = 0; i < port_width; ++i)
data = (data << 8) | *src++;
if ((rc =
write_data(info,
(ulong) ((FPWV *) wp),
(FPW) (data))) != 0)
return (rc);
wp += port_width;
cnt -= port_width;
if (count++ > 0x800) {
spin_wheel();
count = 0;
}
}
}
if (cnt == 0)
return ERR_OK;
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < port_width && cnt > 0;
++i, ++cp) {
data = (data << 8) | (*src++);
--cnt;
}
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return write_data(info, (ulong) ((FPWV *) wp),
(FPW) data);
} /* case FLASH_MAN_INTEL */
} /* switch */
return ERR_OK;
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_data_block(flash_info_t * info, ulong src, ulong dest)
{
FPWV *srcaddr = (FPWV *) src;
FPWV *dstaddr = (FPWV *) dest;
ulong start;
int flag, i;
/* Check if Flash is (sufficiently) erased */
for (i = 0; i < WR_BLOCK; i++)
if ((*dstaddr++ & 0xff) != 0xff) {
printf("not erased at %08lx (%lx)\n",
(ulong) dstaddr, *dstaddr);
return (2);
}
dstaddr = (FPWV *) dest;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*dstaddr = (FPW) INTEL_WRBLK; /* write block setup */
if (flag)
enable_interrupts();
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
return (1);
}
}
*dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */
for (i = 0; i < WR_BLOCK; i++)
*dstaddr++ = *srcaddr++;
dstaddr -= 1;
*dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
return (1);
}
}
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
return (0);
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_data(flash_info_t * info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *) dest;
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf("not erased at %08lx (%lx)\n", (ulong) addr,
(ulong) * addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = (int)disable_interrupts();
*addr = (FPW) INTEL_CLEAR;
*addr = (FPW) INTEL_RESET;
*addr = (FPW) INTEL_WRSETUP; /* write setup */
*addr = data;
if (flag)
enable_interrupts();
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*addr = (FPW) INTEL_SUSERASE; /* suspend mode */
*addr = (FPW) INTEL_CLEAR; /* clear status */
*addr = (FPW) INTEL_RESET; /* reset */
return (1);
}
}
*addr = (FPW) INTEL_CLEAR; /* clear status */
*addr = (FPW) INTEL_RESET; /* restore read mode */
return (0);
}
/*-----------------------------------------------------------------------
* Write a word to Flash for ATMEL FLASH
* A word is 16 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data)
{
ulong start;
int flag, i;
int res = 0; /* result, assume success */
FPWV *base; /* first address in flash bank */
/* Check if Flash is (sufficiently) erased */
if ((*((volatile u16 *)dest) & data) != data) {
return (2);
}
base = (FPWV *) (CFG_ATMEL_BASE);
for (i = 0; i < sizeof(u16); i++) {
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer(0);
/* data polling for D7 */
while (res == 0
&& (*dest & (u8) 0x00800080) !=
(data & (u8) 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*dest = (u8) 0x00F000F0; /* reset bank */
res = 1;
}
}
*dest++ = (u8) 0x00F000F0; /* reset bank */
data >>= 8;
}
return (res);
}
void inline spin_wheel(void)
{
static int p = 0;
static char w[] = "\\/-";
printf("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}
#ifdef CFG_FLASH_PROTECTION
/*-----------------------------------------------------------------------
*/
int flash_real_protect(flash_info_t * info, long sector, int prot)
{
int rcode = 0; /* assume success */
FPWV *addr; /* address of sector */
FPW value;
addr = (FPWV *) (info->start[sector]);
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F160C3B:
case FLASH_28F160C3T:
case FLASH_28F320C3B:
case FLASH_28F320C3T:
case FLASH_28F640C3B:
case FLASH_28F640C3T:
*addr = (FPW) INTEL_RESET; /* make sure in read mode */
*addr = (FPW) INTEL_LOCKBIT; /* lock command setup */
if (prot)
*addr = (FPW) INTEL_PROTECT; /* lock sector */
else
*addr = (FPW) INTEL_CONFIRM; /* unlock sector */
/* now see if it really is locked/unlocked as requested */
*addr = (FPW) INTEL_READID;
/* read sector protection at sector address, (A7 .. A0) = 0x02.
* D0 = 1 for each device if protected.
* If at least one device is protected the sector is marked
* protected, but return failure. Mixed protected and
* unprotected devices within a sector should never happen.
*/
value = addr[2] & (FPW) INTEL_PROTECT;
if (value == 0)
info->protect[sector] = 0;
else if (value == (FPW) INTEL_PROTECT)
info->protect[sector] = 1;
else {
/* error, mixed protected and unprotected */
rcode = 1;
info->protect[sector] = 1;
}
if (info->protect[sector] != prot)
rcode = 1; /* failed to protect/unprotect as requested */
/* reload all protection bits from hardware for now */
flash_sync_real_protect(info);
break;
default:
/* no hardware protect that we support */
info->protect[sector] = prot;
break;
}
return rcode;
}
#endif
#endif

165
board/freescale/m54455evb/m54455evb.c Normal file
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@ -0,0 +1,165 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale M54455 EVB\n");
return 0;
};
long int initdram(int board_type)
{
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 dramsize, i;
dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
gpio->mscr_sdram = 0xAA;
sdram->sdcs0 = (CFG_SDRAM_BASE | i);
sdram->sdcs1 = (CFG_SDRAM_BASE1 | i);
sdram->sdcfg1 = CFG_SDRAM_CFG1;
sdram->sdcfg2 = CFG_SDRAM_CFG2;
/* Issue PALL */
sdram->sdcr = CFG_SDRAM_CTRL | 2;
/* Issue LEMR */
sdram->sdmr = CFG_SDRAM_EMOD | 0x408;
sdram->sdmr = CFG_SDRAM_MODE | 0x300;
udelay(500);
/* Issue PALL */
sdram->sdcr = CFG_SDRAM_CTRL | 2;
/* Perform two refresh cycles */
sdram->sdcr = CFG_SDRAM_CTRL | 4;
sdram->sdcr = CFG_SDRAM_CTRL | 4;
sdram->sdmr = CFG_SDRAM_MODE | 0x200;
sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100);
return (dramsize << 1);
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}
#if defined(CONFIG_CMD_IDE)
#include <ata.h>
int ide_preinit(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10;
gpio->par_feci2c |=
(gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
gpio->par_ata |=
(GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
| GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
GPIO_PAR_ATA_IORDY_IORDY);
gpio->par_pci |=
(GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
return (0);
}
void ide_set_reset(int idereset)
{
volatile atac_t *ata = (atac_t *) MMAP_ATA;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = {
{70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
{25, 70, 20, 10, 20, 5, 10, 0, 35}
}; /* PIO 4 */
if (idereset) {
ata->cr = 0; /* control reset */
udelay(10000);
} else {
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / gd->bus_clk; /* period in ns */
/*ata->ton = CALC_TIMING (180); */
ata->t1 = CALC_TIMING(piotms[2][0]);
ata->t2w = CALC_TIMING(piotms[2][1]);
ata->t2r = CALC_TIMING(piotms[2][1]);
ata->ta = CALC_TIMING(piotms[2][8]);
ata->trd = CALC_TIMING(piotms[2][7]);
ata->t4 = CALC_TIMING(piotms[2][3]);
ata->t9 = CALC_TIMING(piotms[2][6]);
ata->cr = 0x40; /* IORDY enable */
udelay(200000);
ata->cr |= 0x01; /* IORDY enable */
}
}
#endif
#if defined(CONFIG_PCI)
/*
* Initialize PCI devices, report devices found.
*/
static struct pci_controller hose;
extern void pci_mcf5445x_init(struct pci_controller *hose);
void pci_init_board(void)
{
pci_mcf5445x_init(&hose);
}
#endif /* CONFIG_PCI */

320
board/freescale/m54455evb/mii.c Normal file
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/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CFG_FEC0_IOBASE)
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
else
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CFG_FEC0_IOBASE)
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
else
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
}
return 0;
}
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
struct eth_device *dev;
int i, miispd;
u16 rst = 0;
dev = eth_get_dev();
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
for (i = 0; i < FEC_RESET_DELAY; ++i) {
udelay(500);
miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
if ((rst & PHY_BMCR_RESET) == 0)
break;
}
if (i == FEC_RESET_DELAY)
printf("Mii reset timeout %d\n", i);
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
strcpy(info->phy_name,
STR_ID_DP83848VV);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
printf(STR_ID_DP83848VV);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

144
board/freescale/m54455evb/u-boot.lds Normal file
View file

@ -0,0 +1,144 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf5445x/start.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

22
common/cmd_bdinfo.c
View file

@ -208,24 +208,36 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#elif defined(CONFIG_M68K) /* M68K */
static void print_str(const char *, const char *);
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int i;
bd_t *bd = gd->bd;
char buf[32];
print_num ("memstart", (ulong)bd->bi_memstart);
print_num ("memsize", (ulong)bd->bi_memsize);
print_num ("flashstart", (ulong)bd->bi_flashstart);
print_num ("flashsize", (ulong)bd->bi_flashsize);
print_num ("flashoffset", (ulong)bd->bi_flashoffset);
#if defined(CFG_INIT_RAM_ADDR)
print_num ("sramstart", (ulong)bd->bi_sramstart);
print_num ("sramsize", (ulong)bd->bi_sramsize);
print_num ("sramstart", (ulong)bd->bi_sramstart);
print_num ("sramsize", (ulong)bd->bi_sramsize);
#endif
#if defined(CFG_MBAR)
print_num ("mbar", bd->bi_mbar_base );
print_num ("mbar", bd->bi_mbar_base);
#endif
#if defined(CONFIG_CMD_NET)
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
#ifdef CONFIG_PCI
print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq));
#endif
#ifdef CONFIG_EXTRA_CLOCK
print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq));
print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq));
print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq));
#endif
#if defined(CFG_CMD_NET)
puts ("ethaddr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
@ -323,7 +335,7 @@ static void print_num(const char *name, ulong value)
printf ("%-12s= 0x%08lX\n", name, value);
}
#ifdef CONFIG_PPC
#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
static void print_str(const char *name, const char *str)
{
printf ("%-12s= %6s MHz\n", name, str);

48
cpu/mcf5445x/Makefile Normal file
View file

@ -0,0 +1,48 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
# CFLAGS += -DET_DEBUG
LIB = lib$(CPU).a
START = start.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

27
cpu/mcf5445x/config.mk Normal file
View file

@ -0,0 +1,27 @@
#
# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
PLATFORM_CPPFLAGS += -m5407 -fPIC

97
cpu/mcf5445x/cpu.c Normal file
View file

@ -0,0 +1,97 @@
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
rcm->rcr |= RCM_RCR_SOFTRST;
/* we don't return! */
return 0;
};
int checkcpu(void)
{
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts("CPU: ");
msk = (ccm->cir >> 6);
ver = (ccm->cir & 0x003f);
switch (msk) {
case 0x48:
id = 54455;
break;
case 0x49:
id = 54454;
break;
case 0x4a:
id = 54453;
break;
case 0x4b:
id = 54452;
break;
case 0x4d:
id = 54451;
break;
case 0x4f:
id = 54450;
break;
}
if (id) {
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n",
(int)(gd->cpu_clk / 1000000),
(int)(gd->bus_clk / 1000000),
(int)(gd->flb_clk / 1000000));
#ifdef CONFIG_PCI
printf(" PCI CLK %d Mhz INP CLK %d Mhz VCO CLK %d Mhz\n",
(int)(gd->pci_clk / 1000000),
(int)(gd->inp_clk / 1000000),
(int)(gd->vco_clk / 1000000));
#else
printf(" INP CLK %d Mhz VCO CLK %d Mhz\n",
(int)(gd->inp_clk / 1000000),
(int)(gd->vco_clk / 1000000));
#endif
}
return 0;
}

140
cpu/mcf5445x/cpu_init.c Normal file
View file

@ -0,0 +1,140 @@
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/rtc.h>
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
scm1->mpr = 0x77777777;
scm1->pacra = 0;
scm1->pacrb = 0;
scm1->pacrc = 0;
scm1->pacrd = 0;
scm1->pacre = 0;
scm1->pacrf = 0;
scm1->pacrg = 0;
/* FlexBus */
gpio->par_be =
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
GPIO_PAR_BE_BE0_BE0;
gpio->par_fbctl =
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
GPIO_PAR_FBCTL_TS_TS;
#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
fbcs->csar0 = CFG_CS0_BASE;
fbcs->cscr0 = CFG_CS0_CTRL;
fbcs->csmr0 = CFG_CS0_MASK;
#endif
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
/* Latch chipselect */
fbcs->csar1 = CFG_CS1_BASE;
fbcs->cscr1 = CFG_CS1_CTRL;
fbcs->csmr1 = CFG_CS1_MASK;
#endif
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
fbcs->csar2 = CFG_CS2_BASE;
fbcs->cscr2 = CFG_CS2_CTRL;
fbcs->csmr2 = CFG_CS2_MASK;
#endif
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
fbcs->csar3 = CFG_CS3_BASE;
fbcs->cscr3 = CFG_CS3_CTRL;
fbcs->csmr3 = CFG_CS3_MASK;
#endif
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
fbcs->csar4 = CFG_CS4_BASE;
fbcs->cscr4 = CFG_CS4_CTRL;
fbcs->csmr4 = CFG_CS4_MASK;
#endif
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
fbcs->csar5 = CFG_CS5_BASE;
fbcs->cscr5 = CFG_CS5_CTRL;
fbcs->csmr5 = CFG_CS5_MASK;
#endif
#ifdef CONFIG_FSL_I2C
gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
#endif
icache_enable();
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r(void)
{
#ifdef CONFIG_MCFTMR
volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
u32 oscillator = CFG_RTC_OSCILLATOR;
rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
#endif
return (0);
}
void uart_port_conf(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
case 0:
gpio->par_uart =
(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
gpio->par_uart =
(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
break;
}
}

52
cpu/mcf5445x/interrupts.c Normal file
View file

@ -0,0 +1,52 @@
/*
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrh0 |= 0xFFFFFFFF;
intp->imrl0 |= 0xFFFFFFFF;
enable_interrupts();
return 0;
}
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
intp->imrh0 &= ~CFG_TMRINTR_MASK;
}
#endif

189
cpu/mcf5445x/pci.c Normal file
View file

@ -0,0 +1,189 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCI Configuration space access support
*/
#include <common.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/immap.h>
#if defined(CONFIG_PCI)
/* System RAM mapped over PCI */
#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#define cfg_read(val, addr, type, op) *val = op((type)(addr));
#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
#define PCI_OP(rw, size, type, op, mask) \
int pci_##rw##_cfg_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
u32 addr = 0; \
u16 cfg_type = 0; \
addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
out_be32(hose->cfg_addr, addr); \
__asm__ __volatile__("nop"); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
out_be32(hose->cfg_addr, addr & 0x7fffffff); \
__asm__ __volatile__("nop"); \
return 0; \
}
PCI_OP(read, byte, u8 *, in_8, 3)
PCI_OP(read, word, u16 *, in_le16, 2)
PCI_OP(write, byte, u8, out_8, 3)
PCI_OP(write, word, u16, out_le16, 2)
PCI_OP(write, dword, u32, out_le32, 0)
int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
int offset, u32 * val)
{
u32 addr;
u32 tmpv;
u32 mask = 2; /* word access */
/* Read lower 16 bits */
addr = ((offset & 0xfc) | (dev) | 0x80000000);
out_be32(hose->cfg_addr, addr);
__asm__ __volatile__("nop");
*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
out_be32(hose->cfg_addr, addr & 0x7fffffff);
__asm__ __volatile__("nop");
/* Read upper 16 bits */
offset += 2;
addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
out_be32(hose->cfg_addr, addr);
__asm__ __volatile__("nop");
tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
out_be32(hose->cfg_addr, addr & 0x7fffffff);
__asm__ __volatile__("nop");
/* combine results into dword value */
*val = (tmpv << 16) | *val;
return 0;
}
void pci_mcf5445x_init(struct pci_controller *hose)
{
volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u32 barEn = 0;
pciarb->acr = 0x001f001f;
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
PCIREQ2, PCIGNT2 */
gpio->par_pci =
GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
pci->tcr1 |= PCI_TCR1_P;
/* Initiator windows */
pci->iw0btar = CFG_PCI_MEM_PHYS;
pci->iw1btar = CFG_PCI_IO_PHYS;
pci->iw2btar = CFG_PCI_CFG_PHYS;
pci->iwcr =
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
/* Enable bus master and mem access */
pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M;
/* Cache line size and master latency */
pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF);
pci->cr2 = 0;
#ifdef CFG_PCI_BAR0
pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
barEn |= PCI_TCR1_B0E;
#endif
#ifdef CFG_PCI_BAR1
pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
barEn |= PCI_TCR1_B1E;
#endif
#ifdef CFG_PCI_BAR2
pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
barEn |= PCI_TCR1_B2E;
#endif
#ifdef CFG_PCI_BAR3
pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
barEn |= PCI_TCR1_B3E;
#endif
#ifdef CFG_PCI_BAR4
pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
barEn |= PCI_TCR1_B4E;
#endif
#ifdef CFG_PCI_BAR5
pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
barEn |= PCI_TCR1_B5E;
#endif
pci->tcr2 = barEn;
/* Deassert reset bit */
pci->gscr &= ~PCI_GSCR_PR;
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
CFG_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI */

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cpu/mcf5445x/speed.c Normal file
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/*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Low Power Divider specifications
*/
#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
#define CLOCK_PLL_FVCO_MAX 540000000
#define CLOCK_PLL_FVCO_MIN 300000000
#define CLOCK_PLL_FSYS_MAX 266666666
#define CLOCK_PLL_FSYS_MIN 100000000
#define MHZ 1000000
void clock_enter_limp(int lpdiv)
{
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
int i, j;
/* Check bounds of divider */
if (lpdiv < CLOCK_LPD_MIN)
lpdiv = CLOCK_LPD_MIN;
if (lpdiv > CLOCK_LPD_MAX)
lpdiv = CLOCK_LPD_MAX;
/* Round divider down to nearest power of two */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
/* Apply the divider to the system clock */
ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
/* Enable Limp Mode */
ccm->misccr |= CCM_MISCCR_LIMP;
}
/*
* brief Exit Limp mode
* warning The PLL should be set and locked prior to exiting Limp mode
*/
void clock_exit_limp(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
/* Exit Limp mode */
ccm->misccr &= ~CCM_MISCCR_LIMP;
/* Wait for the PLL to lock */
while (!(pll->psr & PLL_PSR_LOCK)) ;
}
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
int get_clocks(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14);
int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
int pllmult_pci[] = { 12, 6, 16, 8 };
int vco, bPci, temp, fbtemp, pcrvalue;
int *pPllmult = NULL;
u16 fbpll_mask;
u8 cpldmode;
/* To determine PCI is present or not */
if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
pPllmult = &pllmult_pci[0];
fbpll_mask = 3;
bPci = 1;
} else {
pPllmult = &pllmult_nopci[0];
fbpll_mask = 7;
#ifdef CONFIG_PCI
gd->pci_clk = 0;
#endif
bPci = 0;
}
#ifdef CONFIG_M54455EVB
/* Temporary place here, belongs in board/freescale/... */
/* Temporary read from CCR- fixed fb issue, must be the same clock
as pci or input clock, causing cpld/fpga read inconsistancy */
fbtemp = pPllmult[ccm->ccr & fbpll_mask];
/* Break down into small pieces, code still in flex bus */
pcrvalue = pll->pcr & 0xFFFFF0FF;
temp = fbtemp - 1;
pcrvalue |= PLL_PCR_OUTDIV3(temp);
pll->pcr = pcrvalue;
cpldmode = *cpld & 0x03;
if (cpldmode == 0) {
/* RCON mode */
vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* invaild range, re-set in PCR */
int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
int i, j, bus;
j = (pll->pcr & 0xFF000000) >> 24;
for (i = j; i < 0xFF; i++) {
vco = i * CFG_INPUT_CLKSRC;
if (vco >= CLOCK_PLL_FVCO_MIN) {
bus = vco / temp;
if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
continue;
else
break;
}
}
pcrvalue = pll->pcr & 0x00FF00FF;
fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
pcrvalue |= ((i << 24) | fbtemp);
pll->pcr = pcrvalue;
}
gd->vco_clk = vco; /* Vco clock */
} else if (cpldmode == 2) {
/* Normal mode */
vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC;
gd->vco_clk = vco; /* Vco clock */
} else if (cpldmode == 3) {
/* serial mode */
}
#endif /* CONFIG_M54455EVB */
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */
temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
gd->bus_clk = vco / temp; /* bus clock */
temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
gd->flb_clk = vco / temp; /* FlexBus clock */
#ifdef CONFIG_PCI
if (bPci) {
temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
gd->pci_clk = vco / temp; /* PCI clock */
}
#endif
}
return (0);
}

388
cpu/mcf5445x/start.S Normal file
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/*
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
/* last three long word reserved for cache status */
#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
#define _START _start
#define _FAULT _fault
#define SAVE_ALL \
move.w #0x2700,%sr; /* disable intrs */ \
subl #60,%sp; /* space for 15 regs */ \
moveml %d0-%d7/%a0-%a6,%sp@;
#define RESTORE_ALL \
moveml %sp@,%d0-%d7/%a0-%a6; \
addl #60,%sp; /* space for 15 regs */ \
rte;
.text
/*
* Vector table. This is used for initial platform startup.
* These vectors are to catch any un-intended traps.
*/
_vectors:
INITSP: .long 0x00000000 /* Initial SP */
INITPC: .long _START /* Initial PC */
vector02: .long _FAULT /* Access Error */
vector03: .long _FAULT /* Address Error */
vector04: .long _FAULT /* Illegal Instruction */
vector05: .long _FAULT /* Reserved */
vector06: .long _FAULT /* Reserved */
vector07: .long _FAULT /* Reserved */
vector08: .long _FAULT /* Privilege Violation */
vector09: .long _FAULT /* Trace */
vector0A: .long _FAULT /* Unimplemented A-Line */
vector0B: .long _FAULT /* Unimplemented F-Line */
vector0C: .long _FAULT /* Debug Interrupt */
vector0D: .long _FAULT /* Reserved */
vector0E: .long _FAULT /* Format Error */
vector0F: .long _FAULT /* Unitialized Int. */
/* Reserved */
vector10_17:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector18: .long _FAULT /* Spurious Interrupt */
vector19: .long _FAULT /* Autovector Level 1 */
vector1A: .long _FAULT /* Autovector Level 2 */
vector1B: .long _FAULT /* Autovector Level 3 */
vector1C: .long _FAULT /* Autovector Level 4 */
vector1D: .long _FAULT /* Autovector Level 5 */
vector1E: .long _FAULT /* Autovector Level 6 */
vector1F: .long _FAULT /* Autovector Level 7 */
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector30_3F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector64_127:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector128_191:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.text
.globl _start
_start:
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
move.l #CFG_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR0
/* initialize general use internal ram */
move.l #0, %d0
move.l #(CACR_STATUS), %a1 /* CACR */
move.l #(ICACHE_STATUS), %a2 /* icache */
move.l #(DCACHE_STATUS), %a3 /* dcache */
move.l %d0, (%a1)
move.l %d0, (%a2)
move.l %d0, (%a3)
/* invalidate and disable cache */
move.l #0x01004100, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
movec %d0, %ACR2
movec %d0, %ACR3
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
bsr cpu_init_f /* run low-level CPU init code (from flash) */
bsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return */
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
link.w %a6,#0
move.l 8(%a6), %sp /* set new stack pointer */
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CFG_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
cmp.l %a1,%a2
bgt.s 1b
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CFG_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CFG_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CFG_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
bgt.s 6b
/*
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CFG_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CFG_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
sub.l #_start,%d1
add.l %a0,%d1
move.l %d1,(%a1)+
cmp.l %a2, %a1
bne 7b
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
jsr (%a1)
/*------------------------------------------------------------------------------*/
/* exception code */
.globl _fault
_fault:
jmp _fault
.globl _exc_handler
_exc_handler:
SAVE_ALL
movel %sp,%sp@-
bsr exc_handler
addql #4,%sp
RESTORE_ALL
.globl _int_handler
_int_handler:
SAVE_ALL
movel %sp,%sp@-
bsr int_handler
addql #4,%sp
RESTORE_ALL
/*------------------------------------------------------------------------------*/
/* cache functions */
.globl icache_enable
icache_enable:
move.l #(CACR_STATUS), %a1 /* read CACR Status */
move.l (%a1), %d1
move.l #0x00040100, %d0 /* Invalidate icache */
or.l %d1, %d0
movec %d0, %CACR
move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup icache */
movec %d0, %ACR2
or.l #0x00088400, %d1 /* Enable bcache and icache */
movec %d1, %CACR
move.l #(ICACHE_STATUS), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
.globl icache_disable
icache_disable:
move.l #(CACR_STATUS), %a1 /* read CACR Status */
move.l (%a1), %d0
and.l #0xFFF77BFF, %d0
or.l #0x00040100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Invalidate icache */
clr.l %d0
movec %d0, %ACR2
movec %d0, %ACR3
move.l #(ICACHE_STATUS), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl icache_status
icache_status:
move.l #(ICACHE_STATUS), %a1
move.l (%a1), %d0
rts
.globl icache_invalid
icache_invalid:
move.l #(CACR_STATUS), %a1 /* read CACR Status */
move.l (%a1), %d0
or.l #0x00040100, %d0 /* Invalidate icache */
movec %d0, %CACR /* Enable and invalidate cache */
rts
.globl dcache_enable
dcache_enable:
move.l #(CACR_STATUS), %a1 /* read CACR Status */
move.l (%a1), %d1
move.l #0x01000000, %d0
or.l %d1, %d0
movec %d0, %CACR /* Invalidate dcache */
move.l #(CFG_SDRAM_BASE + 0xc000), %d0
movec %d0, %ACR0
move.l #0, %d0
movec %d0, %ACR1
or.l #0x80000000, %d1 /* Enable bcache and icache */
movec %d1, %CACR
move.l #(DCACHE_STATUS), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
.globl dcache_disable
dcache_disable:
move.l #(CACR_STATUS), %a1 /* read CACR Status */
move.l (%a1), %d0
and.l #0x7FFFFFFF, %d0
or.l #0x01000000, %d0 /* Setup cache mask */
movec %d0, %CACR /* Disable dcache */
clr.l %d0
movec %d0, %ACR0
movec %d0, %ACR1
move.l #(DCACHE_STATUS), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl dcache_invalid
dcache_invalid:
move.l #(CACR_STATUS), %a1 /* read CACR Status */
move.l (%a1), %d0
or.l #0x01000000, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable and invalidate cache */
rts
.globl dcache_status
dcache_status:
move.l #(DCACHE_STATUS), %a1
move.l (%a1), %d0
rts
/*------------------------------------------------------------------------------*/
.globl version_string
version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"

416
doc/README.m54455evb Normal file
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Freescale MCF54455EVB ColdFire Development Board
================================================
TsiChung Liew(Tsi-Chung.Liew@freescale.com)
Created 4/08/07
===========================================
Changed files:
==============
- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init
- board/freescale/m54455evb/flash.c Atmel and INTEL flash support
- board/freescale/m54455evb/Makefile Makefile
- board/freescale/m54455evb/config.mk config make
- board/freescale/m54455evb/u-boot.lds Linker description
- common/cmd_bdinfo.c Clock frequencies output
- common/cmd_mii.c mii support
- cpu/mcf5445x/cpu.c cpu specific code
- cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
- cpu/mcf5445x/interrupts.c cpu specific interrupt support
- cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
- cpu/mcf5445x/Makefile Makefile
- cpu/mcf5445x/config.mk config make
- cpu/mcf5445x/start.S start up assembly code
- doc/README.m54455evb This readme file
- drivers/net/mcffec.c ColdFire common FEC driver
- drivers/serial/mcfuart.c ColdFire common UART driver
- include/asm-m68k/bitops.h Bit operation function export
- include/asm-m68k/byteorder.h Byte order functions
- include/asm-m68k/fec.h FEC structure and definition
- include/asm-m68k/fsl_i2c.h I2C structure and definition
- include/asm-m68k/global_data.h Global data structure
- include/asm-m68k/immap.h ColdFire specific header file and driver macros
- include/asm-m68k/immap_5445x.h mcf5445x specific header file
- include/asm-m68k/io.h io functions
- include/asm-m68k/m5445x.h mcf5445x specific header file
- include/asm-m68k/posix_types.h Posix
- include/asm-m68k/processor.h header file
- include/asm-m68k/ptrace.h Exception structure
- include/asm-m68k/rtc.h Realtime clock header file
- include/asm-m68k/string.h String function export
- include/asm-m68k/timer.h Timer structure and definition
- include/asm-m68k/types.h Data types definition
- include/asm-m68k/uart.h Uart structure and definition
- include/asm-m68k/u-boot.h u-boot structure
- include/configs/M54455EVB.h Board specific configuration file
- lib_m68k/board.c board init function
- lib_m68k/cache.c
- lib_m68k/interrupts Coldfire common interrupt functions
- lib_m68k/m68k_linux.c
- lib_m68k/time.c Timer functions (Dma timer and PIT)
- lib_m68k/traps.c Exception init code
- rtc/mcfrtc.c Realtime clock Driver
1 MCF5445x specific Options/Settings
====================================
1.1 pre-loader is no longer suppoer in thie coldfire family
1.2 Configuration settings for M54455EVB Development Board
CONFIG_MCF5445x -- define for all MCF5445x CPUs
CONFIG_M54455 -- define for all Freescale MCF54455 CPUs
CONFIG_M54455EVB -- define for M54455EVB board
CONFIG_MCFUART -- define to use common CF Uart driver
CFG_UART_PORT -- define UART port number, start with 0, 1 and 2
CONFIG_BAUDRATE -- define UART baudrate
CONFIG_MCFRTC -- define to use common CF RTC driver
CFG_MCFRTC_BASE -- provide base address for RTC in immap.h
CFG_RTC_OSCILLATOR -- define RTC clock frequency
RTC_DEBUG -- define to show RTC debug message
CFG_CMD_DATE -- enable to use date feature in u-boot
CONFIG_MCFFEC -- define to use common CF FEC driver
CONFIG_NET_MULTI -- define to use multi FEC in u-boot
CONFIG_MII -- enable to use MII driver
CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
CFG_DISCOVER_PHY -- enable PHY discovery
CFG_RX_ETH_BUFFER -- Set FEC Receive buffer
CFG_FAULT_ECHO_LINK_DOWN--
CFG_FEC0_PINMUX -- Set FEC0 Pin configuration
CFG_FEC1_PINMUX -- Set FEC1 Pin configuration
CFG_FEC0_MIIBASE -- Set FEC0 MII base register
CFG_FEC1_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
CONFIG_ISO_PARTITION -- enable ISO read/write
CONFIG_DOS_PARTITION -- enable DOS read/write
CONFIG_IDE_RESET -- define ide_reset()
CONFIG_IDE_PREINIT -- define ide_preinit()
CONFIG_ATAPI -- define ATAPI support
CONFIG_LBA48 -- define LBA48 (larger than 120GB) support
CFG_IDE_MAXBUS -- define max channel
CFG_IDE_MAXDEVICE -- define max devices per channel
CFG_ATA_BASE_ADDR -- define ATA base address
CFG_ATA_IDE0_OFFSET -- define ATA IDE0 offset
CFG_ATA_DATA_OFFSET -- define ATA data IO
CFG_ATA_REG_OFFSET -- define for normal register accesses
CFG_ATA_ALT_OFFSET -- define for alternate registers
CFG_ATA_STRIDE -- define for Interval between registers
_IO_BASE -- define for IO base address
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
CONFIG_FSL_I2C -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
CONFIG_SOFT_I2C -- define for I2C bit-banged
CFG_I2C_SPEED -- define for I2C speed
CFG_I2C_SLAVE -- define for I2C slave address
CFG_I2C_OFFSET -- define for I2C base address offset
CFG_IMMR -- define for MBAR offset
CONFIG_PCI -- define for PCI support
CONFIG_PCI_PNP -- define for Plug n play support
CFG_PCI_MEM_BUS -- PCI memory logical offset
CFG_PCI_MEM_PHYS -- PCI memory physical offset
CFG_PCI_MEM_SIZE -- PCI memory size
CFG_PCI_IO_BUS -- PCI IO logical offset
CFG_PCI_IO_PHYS -- PCI IO physical offset
CFG_PCI_IO_SIZE -- PCI IO size
CFG_PCI_CFG_BUS -- PCI Configuration logical offset
CFG_PCI_CFG_PHYS -- PCI Configuration physical offset
CFG_PCI_CFG_SIZE -- PCI Configuration size
CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
CFG_MBAR -- define MBAR offset
CFG_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel
CONFIG_MONITOR_IS_IN_RAM -- Not support
CFG_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
CFG_CSn_BASE -- defines the Chip Select Base register
CFG_CSn_MASK -- defines the Chip Select Mask register
CFG_CSn_CTRL -- defines the Chip Select Control register
CFG_ATMEL_BASE -- defines the Atmel Flash base
CFG_INTEL_BASE -- defines the Intel Flash base
CFG_SDRAM_BASE -- defines the DRAM Base
CFG_SDRAM_BASE1 -- defines the DRAM Base 1
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
2.1. System memory map:
Flash: 0x00000000-0x3FFFFFFF (1024MB)
DDR: 0x40000000-0x7FFFFFFF (1024MB)
SRAM: 0x80000000-0x8FFFFFFF (256MB)
ATA: 0x90000000-0x9FFFFFFF (256MB)
PCI: 0xA0000000-0xBFFFFFFF (512MB)
FlexBus: 0xC0000000-0xDFFFFFFF (512MB)
IP: 0xF0000000-0xFFFFFFFF (256MB)
2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
linux kernel, you can customize it based on your system requirements:
Atmel boot:
Flash0: 0x00000000-0x0007FFFF (512KB)
Flash1: 0x04000000-0x05FFFFFF (32MB)
Intel boot:
Flash0: 0x00000000-0x01FFFFFF (32MB)
Flash1: 0x04000000-0x0407FFFF (512KB)
CPLD: 0x08000000-0x08FFFFFF (16MB)
FPGA: 0x09000000-0x09FFFFFF (16MB)
DDR: 0x40000000-0x4FFFFFFF (256MB)
SRAM: 0x80000000-0x80007FFF (32KB)
IP: 0xFC000000-0xFC0FFFFF (64KB)
3. SWITCH SETTINGS
==================
3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state
SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down
1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active
SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down
SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
4. COMPILATION
==============
4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version)
from codesourcery.com was used. Download it from:
http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
4.2 Compilation
export CROSS_COMPILE=cross-compile-prefix
cd u-boot-1.x.x
make distclean
make M54455EVB_config, or - default to atmel 33Mhz input clock
make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock
make M54455EVB_a33_config, or - default to atmel 33Mhz input clock
make M54455EVB_a66_config, or - default to atmel 66Mhz input clock
make M54455EVB_intel_config, or - default to intel 33Mhz input clock
make M54455EVB_i33_config, or - default to intel 33Mhz input clock
make M54455EVB_i66_config, or - default to intel 66Mhz input clock
make
5. SCREEN DUMP
==============
5.1 M54455EVB Development board
Boot from Atmel (NOTE: May not show exactly the same)
U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08)
CPU: Freescale MCF54455 (Mask:48 Version:1)
CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz
PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz
Board: Freescale M54455 EVB
I2C: ready
DRAM: 256 MB
FLASH: 16.5 MB
In: serial
Out: serial
Err: serial
Net: FEC0, FEC1
IDE: Bus 0: not available
-> print
bootargs=root=/dev/ram rw
bootdelay=1
baudrate=115200
ethaddr=00:e0:0c:bc:e5:60
eth1addr=00:e0:0c:bc:e5:61
hostname=M54455EVB
netdev=eth0
inpclk=33333333
loadaddr=40010000
load=tftp ${loadaddr) ${u-boot}
upd=run load; run prog
prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
ethact=FEC0
mtdids=nor0=M54455EVB-1
mtdparts=M54455EVB-1:16m(user)
u-boot=u-boot54455.bin
filesize=292b4
fileaddr=40010000
gatewayip=192.168.1.1
netmask=255.255.255.0
ipaddr=192.168.1.3
serverip=192.168.1.2
stdin=serial
stdout=serial
stderr=serial
mem=261632k
Environment size: 563/8188 bytes
-> bdinfo
memstart = 0x40000000
memsize = 0x10000000
flashstart = 0x00000000
flashsize = 0x01080000
flashoffset = 0x00000000
sramstart = 0x80000000
sramsize = 0x00008000
mbar = 0xFC000000
busfreq = 133.333 MHz
pcifreq = 33.333 MHz
flbfreq = 66.666 MHz
inpfreq = 33.333 MHz
vcofreq = 533.333 MHz
ethaddr = 00:E0:0C:BC:E5:60
eth1addr = 00:E0:0C:BC:E5:61
ip_addr = 192.168.1.3
baudrate = 115200 bps
->
-> help
? - alias for 'help'
autoscr - run script from memory
base - print or set address offset
bdinfo - print Board Info structure
boot - boot default, i.e., run 'bootcmd'
bootd - boot default, i.e., run 'bootcmd'
bootelf - Boot from an ELF image in memory
bootm - boot application image from memory
bootp - boot image via network using BootP/TFTP protocol
bootvx - Boot vxWorks from an ELF image
cmp - memory compare
coninfo - print console devices and information
cp - memory copy
crc32 - checksum calculation
date - get/set/reset date & time
dcache - enable or disable data cache
diskboot- boot from IDE device
echo - echo args to console
erase - erase FLASH memory
ext2load- load binary file from a Ext2 filesystem
ext2ls - list files in a directory (default /)
fatinfo - print information about filesystem
fatload - load binary file from a dos filesystem
fatls - list files in a directory (default /)
flinfo - print FLASH memory information
fsinfo - print information about filesystems
fsload - load binary file from a filesystem image
go - start application at address 'addr'
help - print online help
icache - enable or disable instruction cache
icrc32 - checksum calculation
ide - IDE sub-system
iloop - infinite loop on address range
imd - i2c memory display
iminfo - print header information for application image
imls - list all images found in flash
imm - i2c memory modify (auto-incrementing)
imw - memory write (fill)
inm - memory modify (constant address)
iprobe - probe to discover valid I2C chip addresses
itest - return true/false on integer compare
loadb - load binary file over serial line (kermit mode)
loads - load S-Record file over serial line
loady - load binary file over serial line (ymodem mode)
loop - infinite loop on address range
ls - list files in a directory (default /)
md - memory display
mii - MII utility commands
mm - memory modify (auto-incrementing)
mtest - simple RAM test
mw - memory write (fill)
nfs - boot image via network using NFS protocol
nm - memory modify (constant address)
pci - list and access PCI Configuration Space
ping - send ICMP ECHO_REQUEST to network host
printenv- print environment variables
protect - enable or disable FLASH write protection
rarpboot- boot image via network using RARP/TFTP protocol
reset - Perform RESET of the CPU
run - run commands in an environment variable
saveenv - save environment variables to persistent storage
setenv - set environment variables
sleep - delay execution for some time
tftpboot- boot image via network using TFTP protocol
version - print monitor version
->bootm 4000000
## Booting image at 04000000 ...
Image Name: Linux Kernel Image
Created: 2007-08-14 15:13:00 UTC
Image Type: M68K Linux Kernel Image (uncompressed)
Data Size: 2301952 Bytes = 2.2 MB
Load Address: 40020000
Entry Point: 40020000
Verifying Checksum ... OK
OK
Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr
erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007
starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB
Built 1 zonelists. Total pages: 32624
Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph
ysmap-flash.0:5M(kernel)ro,-(jffs2)
PID hash table entries: 1024 (order: 10, 4096 bytes)
Console: colour dummy device 80x25
Dentry cache hash table entries: 32768 (order: 4, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 3, 65536 bytes)
Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init)
Mount-cache hash table entries: 1024
NET: Registered protocol family 16
SCSI subsystem initialized
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
TCP established hash table entries: 8192 (order: 2, 32768 bytes)
TCP bind hash table entries: 4096 (order: 1, 16384 bytes)
TCP: Hash tables configured (established 8192 bind 4096)
TCP reno registered
JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered (default)
ColdFire internal UART serial driver version 1.00
ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART
RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
loop: loaded (max 8 devices)
FEC ENET Version 0.2
fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849
eth0: ethernet 00:08:ee:00:e4:19
physmap platform flash device: 01000000 at 04000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
Intel/Sharp Extended Query Table at 0x0031
Using buffer write method
cfi_cmdset_0001: Erase suspend on write enabled
2 cmdlinepart partitions found on MTD device physmap-flash.0
Creating 2 MTD partitions on "physmap-flash.0":
0x00000000-0x00500000 : "kernel"
mtd: Giving out device 0 to kernel
0x00500000-0x01000000 : "jffs2"
mtd: Giving out device 1 to jffs2
mice: PS/2 mouse device common for all mice
i2c /dev entries driver
TCP cubic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
NET: Registered protocol family 15
VFS: Mounted root (jffs2 filesystem).
Setting the hostname to freescale
Mounting filesystems
mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory
Starting syslogd and klogd
Setting up networking on loopback device:
Setting up networking on eth0:
eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
Adding static route for default gateway to 172.27.255.254:
Setting nameserver to 172.27.0.1 in /etc/resolv.conf:
Starting inetd:
/ #

27
drivers/net/mcffec.c
View file

@ -430,20 +430,33 @@ int fec_init(struct eth_device *dev, bd_t * bd)
/* Set station address */
if ((u32) fecp == CFG_FEC0_IOBASE) {
#ifdef CFG_FEC1_IOBASE
volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE);
ea = &bd->bi_enet1addr[0];
fecp1->palr =
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
ea = &bd->bi_enetaddr[0];
fecp->palr =
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp->paur = (ea[4] << 24) | (ea[5] << 16);
} else {
#ifdef CFG_FEC0_IOBASE
volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE);
ea = &bd->bi_enetaddr[0];
fecp0->palr =
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
#ifdef CFG_FEC1_IOBASE
ea = &bd->bi_enet1addr[0];
fecp->palr =
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
}
fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp->paur = (ea[4] << 24) | (ea[5] << 16);
#ifdef ET_DEBUG
printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
#endif
/* Clear unicast address hash table */
fecp->iaur = 0;
fecp->ialr = 0;

8
include/asm-m68k/global_data.h
View file

@ -39,6 +39,14 @@ typedef struct global_data {
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#ifdef CONFIG_PCI
unsigned long pci_clk;
#endif
#ifdef CONFIG_EXTRA_CLOCK
unsigned long inp_clk;
unsigned long vco_clk;
unsigned long flb_clk;
#endif
unsigned long ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long reset_status; /* reset status register at boot */

40
include/asm-m68k/immap.h
View file

@ -170,4 +170,44 @@
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M5329 */
#ifdef CONFIG_M54455
#include <asm/immap_5445x.h>
#include <asm/m5445x.h>
#define CFG_FEC0_IOBASE (MMAP_FEC0)
#define CFG_FEC1_IOBASE (MMAP_FEC1)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
#define CFG_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (6)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CFG_UDELAY_BASE (MMAP_PIT0)
#define CFG_PIT_BASE (MMAP_PIT1)
#define CFG_PIT_PRESCALE (6)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CFG_PCI_BAR0 CFG_SDRAM_BASE
#define CFG_PCI_BAR4 CFG_SDRAM_BASE
#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
#endif
#endif /* CONFIG_M54455 */
#endif /* __IMMAP_H */

937
include/asm-m68k/immap_5445x.h Normal file
View file

@ -0,0 +1,937 @@
/*
* MCF5445x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5445X__
#define __IMMAP_5445X__
/* Module Base Addresses */
#define MMAP_SCM1 0xFC000000
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_FEC0 0xFC030000
#define MMAP_FEC1 0xFC034000
#define MMAP_RTC 0xFC03C000
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_IACK 0xFC054000
#define MMAP_I2C 0xFC058000
#define MMAP_DSPI 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_EPORT 0xFC094000
#define MMAP_WTM 0xFC098000
#define MMAP_SBF 0xFC0A0000
#define MMAP_RCM 0xFC0A0000
#define MMAP_CCM 0xFC0A0000
#define MMAP_GPIO 0xFC0A4000
#define MMAP_PCI 0xFC0A8000
#define MMAP_PCIARB 0xFC0AC000
#define MMAP_RNG 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C4000
#define MMAP_ATA 0x90000000
/*********************************************************************
* ATA
*********************************************************************/
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
u8 rsvd6[106];
} atac_t;
/*********************************************************************
* Cross-bar switch (XBS)
*********************************************************************/
typedef struct xbs {
u8 resv0[0x100];
u32 prs1; /* XBS Priority Register */
u8 resv1[0xC];
u32 crs1; /* XBS Control Register */
u8 resv2[0xEC];
u32 prs2; /* XBS Priority Register */
u8 resv3[0xC];
u32 crs2; /* XBS Control Register */
u8 resv4[0xEC];
u32 prs3; /* XBS Priority Register */
u8 resv5[0xC];
u32 crs3; /* XBS Control Register */
u8 resv6[0xEC];
u32 prs4; /* XBS Priority Register */
u8 resv7[0xC];
u32 crs4; /* XBS Control Register */
u8 resv8[0xEC];
u32 prs5; /* XBS Priority Register */
u8 resv9[0xC];
u32 crs5; /* XBS Control Register */
u8 resv10[0xEC];
u32 prs6; /* XBS Priority Register */
u8 resv11[0xC];
u32 crs6; /* XBS Control Register */
u8 resv12[0xEC];
u32 prs7; /* XBS Priority Register */
u8 resv13[0xC];
u32 crs7; /* XBS Control Register */
} xbs_t;
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
typedef struct fbcs {
u32 csar0; /* Chip-select Address Register */
u32 csmr0; /* Chip-select Mask Register */
u32 cscr0; /* Chip-select Control Register */
u32 csar1; /* Chip-select Address Register */
u32 csmr1; /* Chip-select Mask Register */
u32 cscr1; /* Chip-select Control Register */
u32 csar2; /* Chip-select Address Register */
u32 csmr2; /* Chip-select Mask Register */
u32 cscr2; /* Chip-select Control Register */
u32 csar3; /* Chip-select Address Register */
u32 csmr3; /* Chip-select Mask Register */
u32 cscr3; /* Chip-select Control Register */
} fbcs_t;
/*********************************************************************
* Enhanced DMA (EDMA)
*********************************************************************/
typedef struct edma {
u32 cr;
u32 es;
u8 resv0[0x6];
u16 erq;
u8 resv1[0x6];
u16 eei;
u8 serq;
u8 cerq;
u8 seei;
u8 ceei;
u8 cint;
u8 cerr;
u8 ssrt;
u8 cdne;
u8 resv2[0x6];
u16 intr;
u8 resv3[0x6];
u16 err;
u8 resv4[0xD0];
u8 dchpri0;
u8 dchpri1;
u8 dchpri2;
u8 dchpri3;
u8 dchpri4;
u8 dchpri5;
u8 dchpri6;
u8 dchpri7;
u8 dchpri8;
u8 dchpri9;
u8 dchpri10;
u8 dchpri11;
u8 dchpri12;
u8 dchpri13;
u8 dchpri14;
u8 dchpri15;
u8 resv5[0xEF0];
u32 tcd0_saddr;
u16 tcd0_attr;
u16 tcd0_soff;
u32 tcd0_nbytes;
u32 tcd0_slast;
u32 tcd0_daddr;
union {
u16 tcd0_citer_elink;
u16 tcd0_citer;
};
u16 tcd0_doff;
u32 tcd0_dlast_sga;
union {
u16 tcd0_biter_elink;
u16 tcd0_biter;
};
u16 tcd0_csr;
u32 tcd1_saddr;
u16 tcd1_attr;
u16 tcd1_soff;
u32 tcd1_nbytes;
u32 tcd1_slast;
u32 tcd1_daddr;
union {
u16 tcd1_citer_elink;
u16 tcd1_citer;
};
u16 tcd1_doff;
u32 tcd1_dlast_sga;
union {
u16 tcd1_biter;
u16 tcd1_biter_elink;
};
u16 tcd1_csr;
u32 tcd2_saddr;
u16 tcd2_attr;
u16 tcd2_soff;
u32 tcd2_nbytes;
u32 tcd2_slast;
u32 tcd2_daddr;
union {
u16 tcd2_citer;
u16 tcd2_citer_elink;
};
u16 tcd2_doff;
u32 tcd2_dlast_sga;
union {
u16 tcd2_biter_elink;
u16 tcd2_biter;
};
u16 tcd2_csr;
u32 tcd3_saddr;
u16 tcd3_attr;
u16 tcd3_soff;
u32 tcd3_nbytes;
u32 tcd3_slast;
u32 tcd3_daddr;
union {
u16 tcd3_citer;
u16 tcd3_citer_elink;
};
u16 tcd3_doff;
u32 tcd3_dlast_sga;
union {
u16 tcd3_biter_elink;
u16 tcd3_biter;
};
u16 tcd3_csr;
u32 tcd4_saddr;
u16 tcd4_attr;
u16 tcd4_soff;
u32 tcd4_nbytes;
u32 tcd4_slast;
u32 tcd4_daddr;
union {
u16 tcd4_citer;
u16 tcd4_citer_elink;
};
u16 tcd4_doff;
u32 tcd4_dlast_sga;
union {
u16 tcd4_biter;
u16 tcd4_biter_elink;
};
u16 tcd4_csr;
u32 tcd5_saddr;
u16 tcd5_attr;
u16 tcd5_soff;
u32 tcd5_nbytes;
u32 tcd5_slast;
u32 tcd5_daddr;
union {
u16 tcd5_citer;
u16 tcd5_citer_elink;
};
u16 tcd5_doff;
u32 tcd5_dlast_sga;
union {
u16 tcd5_biter_elink;
u16 tcd5_biter;
};
u16 tcd5_csr;
u32 tcd6_saddr;
u16 tcd6_attr;
u16 tcd6_soff;
u32 tcd6_nbytes;
u32 tcd6_slast;
u32 tcd6_daddr;
union {
u16 tcd6_citer;
u16 tcd6_citer_elink;
};
u16 tcd6_doff;
u32 tcd6_dlast_sga;
union {
u16 tcd6_biter_elink;
u16 tcd6_biter;
};
u16 tcd6_csr;
u32 tcd7_saddr;
u16 tcd7_attr;
u16 tcd7_soff;
u32 tcd7_nbytes;
u32 tcd7_slast;
u32 tcd7_daddr;
union {
u16 tcd7_citer;
u16 tcd7_citer_elink;
};
u16 tcd7_doff;
u32 tcd7_dlast_sga;
union {
u16 tcd7_biter_elink;
u16 tcd7_biter;
};
u16 tcd7_csr;
u32 tcd8_saddr;
u16 tcd8_attr;
u16 tcd8_soff;
u32 tcd8_nbytes;
u32 tcd8_slast;
u32 tcd8_daddr;
union {
u16 tcd8_citer;
u16 tcd8_citer_elink;
};
u16 tcd8_doff;
u32 tcd8_dlast_sga;
union {
u16 tcd8_biter_elink;
u16 tcd8_biter;
};
u16 tcd8_csr;
u32 tcd9_saddr;
u16 tcd9_attr;
u16 tcd9_soff;
u32 tcd9_nbytes;
u32 tcd9_slast;
u32 tcd9_daddr;
union {
u16 tcd9_citer_elink;
u16 tcd9_citer;
};
u16 tcd9_doff;
u32 tcd9_dlast_sga;
union {
u16 tcd9_biter_elink;
u16 tcd9_biter;
};
u16 tcd9_csr;
u32 tcd10_saddr;
u16 tcd10_attr;
u16 tcd10_soff;
u32 tcd10_nbytes;
u32 tcd10_slast;
u32 tcd10_daddr;
union {
u16 tcd10_citer_elink;
u16 tcd10_citer;
};
u16 tcd10_doff;
u32 tcd10_dlast_sga;
union {
u16 tcd10_biter;
u16 tcd10_biter_elink;
};
u16 tcd10_csr;
u32 tcd11_saddr;
u16 tcd11_attr;
u16 tcd11_soff;
u32 tcd11_nbytes;
u32 tcd11_slast;
u32 tcd11_daddr;
union {
u16 tcd11_citer;
u16 tcd11_citer_elink;
};
u16 tcd11_doff;
u32 tcd11_dlast_sga;
union {
u16 tcd11_biter;
u16 tcd11_biter_elink;
};
u16 tcd11_csr;
u32 tcd12_saddr;
u16 tcd12_attr;
u16 tcd12_soff;
u32 tcd12_nbytes;
u32 tcd12_slast;
u32 tcd12_daddr;
union {
u16 tcd12_citer;
u16 tcd12_citer_elink;
};
u16 tcd12_doff;
u32 tcd12_dlast_sga;
union {
u16 tcd12_biter;
u16 tcd12_biter_elink;
};
u16 tcd12_csr;
u32 tcd13_saddr;
u16 tcd13_attr;
u16 tcd13_soff;
u32 tcd13_nbytes;
u32 tcd13_slast;
u32 tcd13_daddr;
union {
u16 tcd13_citer_elink;
u16 tcd13_citer;
};
u16 tcd13_doff;
u32 tcd13_dlast_sga;
union {
u16 tcd13_biter_elink;
u16 tcd13_biter;
};
u16 tcd13_csr;
u32 tcd14_saddr;
u16 tcd14_attr;
u16 tcd14_soff;
u32 tcd14_nbytes;
u32 tcd14_slast;
u32 tcd14_daddr;
union {
u16 tcd14_citer;
u16 tcd14_citer_elink;
};
u16 tcd14_doff;
u32 tcd14_dlast_sga;
union {
u16 tcd14_biter_elink;
u16 tcd14_biter;
};
u16 tcd14_csr;
u32 tcd15_saddr;
u16 tcd15_attr;
u16 tcd15_soff;
u32 tcd15_nbytes;
u32 tcd15_slast;
u32 tcd15_daddr;
union {
u16 tcd15_citer_elink;
u16 tcd15_citer;
};
u16 tcd15_doff;
u32 tcd15_dlast_sga;
union {
u16 tcd15_biter;
u16 tcd15_biter_elink;
};
u16 tcd15_csr;
} edma_t;
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/*********************************************************************
* Global Interrupt Acknowledge (IACK)
*********************************************************************/
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 resv1[0x3];
u8 gl1iack;
u8 resv2[0x3];
u8 gl2iack;
u8 resv3[0x3];
u8 gl3iack;
u8 resv4[0x3];
u8 gl4iack;
u8 resv5[0x3];
u8 gl5iack;
u8 resv6[0x3];
u8 gl6iack;
u8 resv7[0x3];
u8 gl7iack;
} iack_t;
/*********************************************************************
* DMA Serial Peripheral Interface (DSPI)
*********************************************************************/
typedef struct dspi {
u32 dmcr;
u8 resv0[0x4];
u32 dtcr;
u32 dctar0;
u32 dctar1;
u32 dctar2;
u32 dctar3;
u32 dctar4;
u32 dctar5;
u32 dctar6;
u32 dctar7;
u32 dsr;
u32 dirsr;
u32 dtfr;
u32 drfr;
u32 dtfdr0;
u32 dtfdr1;
u32 dtfdr2;
u32 dtfdr3;
u8 resv1[0x30];
u32 drfdr0;
u32 drfdr1;
u32 drfdr2;
u32 drfdr3;
} dspi_t;
/*********************************************************************
* Edge Port Module (EPORT)
*********************************************************************/
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epier;
u8 epdr;
u8 eppdr;
u8 epfr;
} eport_t;
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
typedef struct wtm {
u16 wcr;
u16 wmr;
u16 wcntr;
u16 wsr;
} wtm_t;
/*********************************************************************
* Serial Boot Facility (SBF)
*********************************************************************/
typedef struct sbf {
u8 resv0[0x18];
u16 sbfsr; /* Serial Boot Facility Status Register */
u8 resv1[0x6];
u16 sbfcr; /* Serial Boot Facility Control Register */
} sbf_t;
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
typedef struct ccm {
u8 ccm_resv0[0x4];
u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
u8 resv1[0x2];
u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
u16 cir; /* Chip Identification Register (Read-only) */
u8 resv2[0x4];
u16 misccr; /* Miscellaneous Control Register */
u16 cdr; /* Clock Divider Register */
u16 uocsr; /* USB On-the-Go Controller Status Register */
} ccm_t;
/*********************************************************************
* General Purpose I/O Module (GPIO)
*********************************************************************/
typedef struct gpio {
u8 podr_fec0h; /* FEC0 High Port Output Data Register */
u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
u8 podr_ssi; /* SSI Port Output Data Register */
u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
u8 podr_dma; /* DMA Port Output Data Register */
u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
u8 resv0[0x1];
u8 podr_uart; /* UART Port Output Data Register */
u8 podr_dspi; /* DSPI Port Output Data Register */
u8 podr_timer; /* Timer Port Output Data Register */
u8 podr_pci; /* PCI Port Output Data Register */
u8 podr_usb; /* USB Port Output Data Register */
u8 podr_atah; /* ATA High Port Output Data Register */
u8 podr_atal; /* ATA Low Port Output Data Register */
u8 podr_fec1h; /* FEC1 High Port Output Data Register */
u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
u8 resv1[0x2];
u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
u8 pddr_ssi; /* SSI Port Data Direction Register */
u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
u8 pddr_dma; /* DMA Port Data Direction Register */
u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
u8 resv2[0x1];
u8 pddr_uart; /* UART Port Data Direction Register */
u8 pddr_dspi; /* DSPI Port Data Direction Register */
u8 pddr_timer; /* Timer Port Data Direction Register */
u8 pddr_pci; /* PCI Port Data Direction Register */
u8 pddr_usb; /* USB Port Data Direction Register */
u8 pddr_atah; /* ATA High Port Data Direction Register */
u8 pddr_atal; /* ATA Low Port Data Direction Register */
u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
u8 resv3[0x2];
u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
u8 resv4[0x1];
u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
u8 resv5[0x2];
u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
u8 pclrr_dma; /* DMA Port Clear Output Data Register */
u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
u8 resv6[0x1];
u8 pclrr_uart; /* UART Port Clear Output Data Register */
u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
u8 pclrr_timer; /* Timer Port Clear Output Data Register */
u8 pclrr_pci; /* PCI Port Clear Output Data Register */
u8 pclrr_usb; /* USB Port Clear Output Data Register */
u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
u8 resv7[0x2];
u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
u8 par_fec; /* FEC Pin Assignment Register */
u8 par_dma; /* DMA Pin Assignment Register */
u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
u8 par_dspi; /* DSPI Pin Assignment Register */
u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
u8 par_timer; /* Time Pin Assignment Register */
u8 par_usb; /* USB Pin Assignment Register */
u8 resv8[0x1];
u8 par_uart; /* UART Pin Assignment Register */
u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
u16 par_ssi; /* SSI Pin Assignment Register */
u16 par_ata; /* ATA Pin Assignment Register */
u8 par_irq; /* IRQ Pin Assignment Register */
u8 resv9[0x1];
u16 par_pci; /* PCI Pin Assignment Register */
u8 mscr_sdram; /* SDRAM Mode Select Control Register */
u8 mscr_pci; /* PCI Mode Select Control Register */
u8 resv10[0x2];
u8 dscr_i2c; /* I2C Drive Strength Control Register */
u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
u8 dscr_fec; /* FEC Drive Strength Control Register */
u8 dscr_uart; /* UART Drive Strength Control Register */
u8 dscr_dspi; /* DSPI Drive Strength Control Register */
u8 dscr_timer; /* TIMER Drive Strength Control Register */
u8 dscr_ssi; /* SSI Drive Strength Control Register */
u8 dscr_dma; /* DMA Drive Strength Control Register */
u8 dscr_debug; /* DEBUG Drive Strength Control Register */
u8 dscr_reset; /* RESET Drive Strength Control Register */
u8 dscr_irq; /* IRQ Drive Strength Control Register */
u8 dscr_usb; /* USB Drive Strength Control Register */
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
/*********************************************************************
* Random Number Generator (RNG)
*********************************************************************/
typedef struct rng {
u32 rngcr;
u32 rngsr;
u32 rnger;
u32 rngout;
} rng_t;
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */
u32 sdcr; /* SDRAM Control Register */
u32 sdcfg1; /* SDRAM Configuration Register 1 */
u32 sdcfg2; /* SDRAM Chip Select Register */
u8 resv0[0x100];
u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
} sdramc_t;
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
typedef struct ssi {
u32 tx0;
u32 tx1;
u32 rx0;
u32 rx1;
u32 cr;
u32 isr;
u32 ier;
u32 tcr;
u32 rcr;
u32 ccr;
u8 resv0[0x4];
u32 fcsr;
u8 resv1[0x8];
u32 acr;
u32 acadd;
u32 acdat;
u32 atag;
u32 tmask;
u32 rmask;
} ssi_t;
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
typedef struct pll {
u32 pcr; /* PLL Control Register */
u32 psr; /* PLL Status Register */
} pll_t;
typedef struct pci {
u32 idr; /* 0x00 Device Id / Vendor Id Register */
u32 scr; /* 0x04 Status / command Register */
u32 ccrir; /* 0x08 Class Code / Revision Id Register */
u32 cr1; /* 0x0c Configuration 1 Register */
u32 bar0; /* 0x10 Base address register 0 Register */
u32 bar1; /* 0x14 Base address register 1 Register */
u32 bar2; /* 0x18 Base address register 2 Register */
u32 bar3; /* 0x1c Base address register 3 Register */
u32 bar4; /* 0x20 Base address register 4 Register */
u32 bar5; /* 0x24 Base address register 5 Register */
u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
u32 erbar; /* 0x30 Expansion ROM Base Address Register */
u32 cpr; /* 0x34 Capabilities Pointer Register */
u32 rsvd1; /* 0x38 */
u32 cr2; /* 0x3c Configuration Register 2 */
u32 rsvd2[8]; /* 0x40 - 0x5f */
/* General control / status registers */
u32 gscr; /* 0x60 Global Status / Control Register */
u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
u32 tcr1; /* 0x6c Target Control 1 Register */
u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
u32 rsvd3; /* 0x7c */
u32 iwcr; /* 0x80 Initiator Window Configuration Register */
u32 icr; /* 0x84 Initiator Control Register */
u32 isr; /* 0x88 Initiator Status Register */
u32 tcr2; /* 0x8c Target Control 2 Register */
u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
u32 intr; /* 0xa8 Interrupt Register */
u32 rsvd4[19]; /* 0xac - 0xf7 */
u32 car; /* 0xf8 Configuration Address Register */
} pci_t;
typedef struct pci_arbiter {
/* Pci Arbiter Registers */
union {
u32 acr; /* Arbiter Control Register */
u32 asr; /* Arbiter Status Register */
};
} pciarb_t;
/* Register read/write struct */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege Register */
u32 rsvd1[7];
u32 pacra; /* 0x20 Peripheral Access Control Register A */
u32 pacrb; /* 0x24 Peripheral Access Control Register B */
u32 pacrc; /* 0x28 Peripheral Access Control Register C */
u32 pacrd; /* 0x2C Peripheral Access Control Register D */
u32 rsvd2[4];
u32 pacre; /* 0x40 Peripheral Access Control Register E */
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
} scm1_t;
/********************************************************************/
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5445X__ */

1541
include/asm-m68k/m5445x.h Normal file
View file

File diff suppressed because it is too large Load diff

3
include/asm-m68k/rtc.h
View file

@ -35,9 +35,10 @@ typedef struct rtc_ctrl {
u32 cr; /* 0x10 Control Register */
u32 isr; /* 0x14 Interrupt Status Register */
u32 ier; /* 0x18 Interrupt Enable Register */
u32 stpwach; /* 0x1C Stopwatch Minutes Register */
u32 stpwatch; /* 0x1C Stopwatch Minutes Register */
u32 days; /* 0x20 Days Counter Register */
u32 alrm_day; /* 0x24 Days Alarm Register */
void *extended;
} rtc_t;
/* Bit definitions and macros for HOURMIN */

8
include/asm-m68k/u-boot.h
View file

@ -52,6 +52,14 @@ typedef struct bd_info {
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
#ifdef CONFIG_PCI
unsigned long bi_pcifreq; /* pci Freq in MHz */
#endif
#ifdef CONFIG_EXTRA_CLOCK
unsigned long bi_inpfreq; /* input Freq in MHz */
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
unsigned long bi_baudrate; /* Console Baudrate */
#ifdef CONFIG_HAS_ETH1

391
include/configs/M54455EVB.h Normal file
View file

@ -0,0 +1,391 @@
/*
* Configuation settings for the Freescale MCF54455 EVB board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _JAMICA54455_H
#define _JAMICA54455_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF5445x /* define processor family */
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CONFIG_CF_DOMII
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC1_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
# define CONFIG_HAS_ETH1
# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
# define CONFIG_ETHPRIME "FEC0"
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
#define CONFIG_HOSTNAME M54455EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 2ffff;" \
"era 0 2ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
/* ATA configuration */
#define CONFIG_ISO_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_IDE_RESET 1
#define CONFIG_IDE_PREINIT 1
#define CONFIG_ATAPI
#undef CONFIG_LBA48
#define CFG_IDE_MAXBUS 1
#define CFG_IDE_MAXDEVICE 2
#define CFG_ATA_BASE_ADDR 0x90000000
#define CFG_ATA_IDE0_OFFSET 0
#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
#define CFG_ATA_STRIDE 4 /* Interval between registers */
#define _IO_BASE 0
/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x58000
#define CFG_IMMR CFG_MBAR
/* PCI */
#define CONFIG_PCI 1
#define CFG_PCI_MEM_BUS 0xA0000000
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
#define CFG_PCI_MEM_SIZE 0x10000000
#define CFG_PCI_IO_BUS 0xB1000000
#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
#define CFG_PCI_IO_SIZE 0x01000000
#define CFG_PCI_CFG_BUS 0xB0000000
#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
#define CFG_PCI_CFG_SIZE 0x01000000
/* FPGA - Spartan 2 */
/* experiment
#define CONFIG_FPGA CFG_SPARTAN3
#define CONFIG_FPGA_COUNT 1
#define CFG_FPGA_PROG_FEEDBACK
#define CFG_FPGA_CHECK_CTRLC
*/
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
#define CFG_HZ 1000
#define CFG_MBAR 0xFC000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x80000000
#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x221
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x40000000
#define CFG_SDRAM_BASE1 0x48000000
#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */
#define CFG_SDRAM_CFG1 0x65311610
#define CFG_SDRAM_CFG2 0x59670000
#define CFG_SDRAM_CTRL 0xEA0B2000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x00010033
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_BOOTPARAMS_LEN 64*1024
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OVERWRITE 1
#undef CFG_ENV_IS_EMBEDDED
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CFG_ATMEL_BOOT
# define CFG_FLASH_BASE 0
# define CFG_FLASH0_BASE CFG_CS0_BASE
# define CFG_FLASH1_BASE CFG_CS1_BASE
#else
# define CFG_FLASH_BASE CFG_FLASH0_BASE
# define CFG_FLASH0_BASE CFG_CS1_BASE
# define CFG_FLASH1_BASE CFG_CS0_BASE
#endif
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
keep reset. */
#undef CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
#else
# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CFG_ATMEL_REGION 4
# define CFG_ATMEL_TOTALSECT 11
# define CFG_ATMEL_SECT {1, 2, 1, 7}
# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
# define CFG_INTEL_SECT 137
/* max number of sectors on one chip */
# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT)
# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */
# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
#endif
/*
* This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#ifdef CFG_ATMEL_BOOT
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE 0x01000000
# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
#else
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - CompactFlash and registers
* CS2 - CPLD
* CS3 - FPGA
* CS4 - Available
* CS5 - Available
*/
#ifdef CFG_ATMEL_BOOT
/* Atmel Flash */
#define CFG_CS0_BASE 0
#define CFG_CS0_MASK 0x00070001
#define CFG_CS0_CTRL 0x00001140
/* Intel Flash */
#define CFG_CS1_BASE 0x04000000
#define CFG_CS1_MASK 0x01FF0001
#define CFG_CS1_CTRL 0x003F3D60
#define CFG_ATMEL_BASE CFG_CS0_BASE
#else
/* Intel Flash */
#define CFG_CS0_BASE 0
#define CFG_CS0_MASK 0x01FF0001
#define CFG_CS0_CTRL 0x003F3D60
/* Atmel Flash */
#define CFG_CS1_BASE 0x04000000
#define CFG_CS1_MASK 0x00070001
#define CFG_CS1_CTRL 0x00001140
#define CFG_ATMEL_BASE CFG_CS1_BASE
#endif
/* CPLD */
#define CFG_CS2_BASE 0x08000000
#define CFG_CS2_MASK 0x00070001
#define CFG_CS2_CTRL 0x003f1140
/* FPGA */
#define CFG_CS3_BASE 0x09000000
#define CFG_CS3_MASK 0x00070001
#define CFG_CS3_CTRL 0x00000020
#endif /* _JAMICA54455_H */

30
lib_m68k/board.c
View file

@ -30,9 +30,7 @@
#include <malloc.h>
#include <devices.h>
#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#endif
#include <asm/immap.h>
#if defined(CONFIG_CMD_IDE)
#include <ide.h>
@ -139,19 +137,19 @@ void *sbrk (ptrdiff_t increment)
char *strmhz(char *buf, long hz)
{
long l, n;
long m;
long l, n;
long m;
n = hz / 1000000L;
n = hz / 1000000L;
l = sprintf (buf, "%ld", n);
l = sprintf (buf, "%ld", n);
m = (hz % 1000000L) / 1000L;
m = (hz % 1000000L) / 1000L;
if (m != 0)
sprintf (buf+l, ".%03ld", m);
if (m != 0)
sprintf (buf+l, ".%03ld", m);
return (buf);
return (buf);
}
/*
@ -169,7 +167,7 @@ char *strmhz(char *buf, long hz)
typedef int (init_fnc_t) (void);
/************************************************************************
* Init Utilities *
* Init Utilities
************************************************************************
* Some of this code should be moved into the core functions,
* but let's get it working (again) first...
@ -383,6 +381,14 @@ board_init_f (ulong bootflag)
WATCHDOG_RESET ();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
#ifdef CONFIG_PCI
bd->bi_pcifreq = gd->pci_clk; /* PCI Freq in Hz */
#endif
#ifdef CONFIG_EXTRA_CLOCK
bd->bi_inpfreq = gd->inp_clk; /* input Freq in Hz */
bd->bi_vcofreq = gd->vco_clk; /* vco Freq in Hz */
bd->bi_flbfreq = gd->flb_clk; /* flexbus Freq in Hz */
#endif
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CFG_EXTBDINFO

0
lib_m68k/interrupts.c Executable file → Normal file
View file

376
lib_m68k/m68k_linux.c
View file

@ -25,6 +25,8 @@
#include <command.h>
#include <image.h>
#include <zlib.h>
#include <bzlib.h>
#include <environment.h>
#include <asm/byteorder.h>
DECLARE_GLOBAL_DATA_PTR;
@ -34,103 +36,189 @@ DECLARE_GLOBAL_DATA_PTR;
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
extern image_header_t header; /* from cmd_bootm.c */
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
#else
# define SHOW_BOOT_PROGRESS(arg)
#endif
extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
extern image_header_t header;
static int linux_argc;
static char **linux_argv;
static char **linux_env;
static char *linux_env_p;
static int linux_env_idx;
static void linux_params_init (ulong start, char *commandline);
static void linux_env_set (char *env_name, char *env_val);
void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
ulong addr, ulong * len_ptr, int verify)
void do_bootm_linux(cmd_tbl_t * cmdtp, int flag,
int argc, char *argv[],
ulong addr, ulong * len_ptr, int verify)
{
ulong len = 0, checksum;
ulong sp;
ulong len, checksum;
ulong initrd_start, initrd_end;
ulong cmd_start, cmd_end;
ulong initrd_high;
ulong data;
void (*theKernel) (int, char **, char **, int *);
int initrd_copy_to_ram = 1;
char *cmdline;
char *s;
bd_t *kbd;
void (*kernel) (bd_t *, ulong, ulong, ulong, ulong);
image_header_t *hdr = &header;
char *commandline = getenv ("bootargs");
char env_buf[12];
theKernel =
(void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep);
if ((s = getenv("initrd_high")) != NULL) {
/* a value of "no" or a similar string will act like 0,
* turning the "load high" feature off. This is intentional.
*/
initrd_high = simple_strtoul(s, NULL, 16);
if (initrd_high == ~0)
initrd_copy_to_ram = 0;
} else { /* not set, no restrictions to load high */
initrd_high = ~0;
}
#ifdef CONFIG_LOGBUFFER
kbd = gd->bd;
/* Prevent initrd from overwriting logbuffer */
if (initrd_high < (kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD))
initrd_high = kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD;
debug("## Logbuffer at 0x%08lX ", kbd->bi_memsize - LOGBUFF_LEN);
#endif
/*
* Booting a (Linux) kernel image
*
* Allocate space for command line and board info - the
* address should be as high as possible within the reach of
* the kernel (see CFG_BOOTMAPSZ settings), but in unused
* memory, which means far enough below the current stack
* pointer.
*/
asm("movel %%a7, %%d0\n"
"movel %%d0, %0\n": "=d"(sp): :"%d0");
debug("## Current stack ends at 0x%08lX ", sp);
sp -= 2048; /* just to be sure */
if (sp > CFG_BOOTMAPSZ)
sp = CFG_BOOTMAPSZ;
sp &= ~0xF;
debug("=> set upper limit to 0x%08lX\n", sp);
cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF);
kbd = (bd_t *) (((ulong) cmdline - sizeof(bd_t)) & ~0xF);
if ((s = getenv("bootargs")) == NULL)
s = "";
strcpy(cmdline, s);
cmd_start = (ulong) & cmdline[0];
cmd_end = cmd_start + strlen(cmdline);
*kbd = *(gd->bd);
#ifdef DEBUG
printf("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end);
do_bdinfo(NULL, 0, 0, NULL);
#endif
if ((s = getenv("clocks_in_mhz")) != NULL) {
/* convert all clock information to MHz */
kbd->bi_intfreq /= 1000000L;
kbd->bi_busfreq /= 1000000L;
}
kernel =
(void (*)(bd_t *, ulong, ulong, ulong, ulong))ntohl(hdr->ih_ep);
/*
* Check if there is an initrd image
*/
if (argc >= 3) {
show_boot_progress (9);
debug("Not skipping initrd\n");
SHOW_BOOT_PROGRESS(9);
addr = simple_strtoul (argv[2], NULL, 16);
addr = simple_strtoul(argv[2], NULL, 16);
printf ("## Loading Ramdisk Image at %08lx ...\n", addr);
printf("## Loading RAMDisk Image at %08lx ...\n", addr);
/* Copy header so we can blank CRC field for re-calculation */
memcpy (&header, (char *) addr, sizeof (image_header_t));
memmove(&header, (char *)addr, sizeof(image_header_t));
if (ntohl (hdr->ih_magic) != IH_MAGIC) {
printf ("Bad Magic Number\n");
show_boot_progress (-10);
do_reset (cmdtp, flag, argc, argv);
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
puts("Bad Magic Number\n");
SHOW_BOOT_PROGRESS(-10);
do_reset(cmdtp, flag, argc, argv);
}
data = (ulong) & header;
len = sizeof (image_header_t);
len = sizeof(image_header_t);
checksum = ntohl (hdr->ih_hcrc);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
if (crc32 (0, (char *) data, len) != checksum) {
printf ("Bad Header Checksum\n");
show_boot_progress (-11);
do_reset (cmdtp, flag, argc, argv);
if (crc32(0, (uchar *) data, len) != checksum) {
puts("Bad Header Checksum\n");
SHOW_BOOT_PROGRESS(-11);
do_reset(cmdtp, flag, argc, argv);
}
show_boot_progress (10);
SHOW_BOOT_PROGRESS(10);
print_image_hdr (hdr);
print_image_hdr(hdr);
data = addr + sizeof (image_header_t);
len = ntohl (hdr->ih_size);
data = addr + sizeof(image_header_t);
len = ntohl(hdr->ih_size);
if (verify) {
ulong csum = 0;
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
ulong cdata = data, edata = cdata + len;
#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
printf (" Verifying Checksum ... ");
csum = crc32 (0, (char *) data, len);
if (csum != ntohl (hdr->ih_dcrc)) {
printf ("Bad Data CRC\n");
show_boot_progress (-12);
do_reset (cmdtp, flag, argc, argv);
puts(" Verifying Checksum ... ");
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
while (cdata < edata) {
ulong chunk = edata - cdata;
if (chunk > CHUNKSZ)
chunk = CHUNKSZ;
csum = crc32(csum, (uchar *) cdata, chunk);
cdata += chunk;
WATCHDOG_RESET();
}
printf ("OK\n");
#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
csum = crc32(0, (uchar *) data, len);
#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
if (csum != ntohl(hdr->ih_dcrc)) {
puts("Bad Data CRC\n");
SHOW_BOOT_PROGRESS(-12);
do_reset(cmdtp, flag, argc, argv);
}
puts("OK\n");
}
show_boot_progress (11);
SHOW_BOOT_PROGRESS(11);
if ((hdr->ih_os != IH_OS_LINUX) ||
(hdr->ih_arch != IH_CPU_M68K) ||
(hdr->ih_type != IH_TYPE_RAMDISK)) {
printf ("No Linux M68K Ramdisk Image\n");
show_boot_progress (-13);
do_reset (cmdtp, flag, argc, argv);
puts("No Linux ColdFire Ramdisk Image\n");
SHOW_BOOT_PROGRESS(-13);
do_reset(cmdtp, flag, argc, argv);
}
/*
* Now check if we have a multifile image
*/
} else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) {
ulong tail = ntohl (len_ptr[0]) % 4;
u_long tail = ntohl(len_ptr[0]) % 4;
int i;
show_boot_progress (13);
SHOW_BOOT_PROGRESS(13);
/* skip kernel length and terminator */
data = (ulong) (&len_ptr[2]);
@ -138,130 +226,110 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
for (i = 1; len_ptr[i]; ++i)
data += 4;
/* add kernel length, and align */
data += ntohl (len_ptr[0]);
data += ntohl(len_ptr[0]);
if (tail) {
data += 4 - tail;
}
len = ntohl (len_ptr[1]);
len = ntohl(len_ptr[1]);
} else {
/*
* no initrd image
*/
show_boot_progress (14);
SHOW_BOOT_PROGRESS(14);
data = 0;
len = data = 0;
}
#ifdef DEBUG
if (!data) {
printf ("No initrd\n");
debug("No initrd\n");
}
#endif
if (data) {
initrd_start = data;
initrd_end = initrd_start + len;
if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */
initrd_start = data;
initrd_end = initrd_start + len;
} else {
initrd_start = (ulong) kbd - len;
initrd_start &= ~(4096 - 1); /* align on page */
if (initrd_high) {
ulong nsp;
/*
* the inital ramdisk does not need to be within
* CFG_BOOTMAPSZ as it is not accessed until after
* the mm system is initialised.
*
* do the stack bottom calculation again and see if
* the initrd will fit just below the monitor stack
* bottom without overwriting the area allocated
* above for command line args and board info.
*/
asm("movel %%a7, %%d0\n"
"movel %%d0, %0\n": "=d"(nsp): :"%d0");
nsp -= 2048; /* just to be sure */
nsp &= ~0xF;
if (nsp > initrd_high) /* limit as specified */
nsp = initrd_high;
nsp -= len;
nsp &= ~(4096 - 1); /* align on page */
if (nsp >= sp)
initrd_start = nsp;
}
SHOW_BOOT_PROGRESS(12);
debug
("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
data, data + len - 1, len, len);
initrd_end = initrd_start + len;
printf(" Loading Ramdisk to %08lx, end %08lx ... ",
initrd_start, initrd_end);
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
{
size_t l = len;
void *to = (void *)initrd_start;
void *from = (void *)data;
while (l > 0) {
size_t tail =
(l > CHUNKSZ) ? CHUNKSZ : l;
WATCHDOG_RESET();
memmove(to, from, tail);
to += tail;
from += tail;
l -= tail;
}
}
#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
memmove((void *)initrd_start, (void *)data, len);
#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
puts("OK\n");
}
} else {
initrd_start = 0;
initrd_end = 0;
}
show_boot_progress (15);
debug("## Transferring control to Linux (at address %08lx) ...\n",
(ulong) kernel);
#ifdef DEBUG
printf ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong) theKernel);
#endif
SHOW_BOOT_PROGRESS(15);
linux_params_init (PHYSADDR (gd->bd->bi_boot_params), commandline);
sprintf (env_buf, "%lu", gd->ram_size >> 20);
linux_env_set ("memsize", env_buf);
sprintf (env_buf, "0x%08X", (uint) PHYSADDR (initrd_start));
linux_env_set ("initrd_start", env_buf);
sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start));
linux_env_set ("initrd_size", env_buf);
sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart));
linux_env_set ("flash_start", env_buf);
sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize));
linux_env_set ("flash_size", env_buf);
/* we assume that the kernel is in place */
printf ("\nStarting kernel ...\n\n");
theKernel (linux_argc, linux_argv, linux_env, 0);
}
static void linux_params_init (ulong start, char *line)
{
char *next, *quote, *argp;
linux_argc = 1;
linux_argv = (char **) start;
linux_argv[0] = 0;
argp = (char *) (linux_argv + LINUX_MAX_ARGS);
next = line;
while (line && *line && linux_argc < LINUX_MAX_ARGS) {
quote = strchr (line, '"');
next = strchr (line, ' ');
while (next != NULL && quote != NULL && quote < next) {
/* we found a left quote before the next blank
* now we have to find the matching right quote
*/
next = strchr (quote + 1, '"');
if (next != NULL) {
quote = strchr (next + 1, '"');
next = strchr (next + 1, ' ');
}
}
if (next == NULL) {
next = line + strlen (line);
}
linux_argv[linux_argc] = argp;
memcpy (argp, line, next - line);
argp[next - line] = 0;
argp += next - line + 1;
linux_argc++;
if (*next)
next++;
line = next;
}
linux_env = (char **) (((ulong) argp + 15) & ~15);
linux_env[0] = 0;
linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS);
linux_env_idx = 0;
}
static void linux_env_set (char *env_name, char *env_val)
{
if (linux_env_idx < LINUX_MAX_ENVS - 1) {
linux_env[linux_env_idx] = linux_env_p;
strcpy (linux_env_p, env_name);
linux_env_p += strlen (env_name);
strcpy (linux_env_p, "=");
linux_env_p += 1;
strcpy (linux_env_p, env_val);
linux_env_p += strlen (env_val);
linux_env_p++;
linux_env[++linux_env_idx] = 0;
}
/*
* Linux Kernel Parameters (passing board info data):
* r3: ptr to board info data
* r4: initrd_start or 0 if no initrd
* r5: initrd_end - unused if r4 is 0
* r6: Start of command line string
* r7: End of command line string
*/
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
/* does not return */
}