mirror of
https://github.com/AsahiLinux/u-boot
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550650ddd0
This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
443 lines
15 KiB
C
443 lines
15 KiB
C
/*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405EP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_PLU405 1 /* ...on a PLU405 board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
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#define CONFIG_BAUDRATE 9600
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#undef CONFIG_BOOTARGS
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_PREBOOT /* enable preboot variable */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_USB
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SUPPORT_VFAT
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
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#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
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#define CONFIG_SYS_BASE_BAUD 691200
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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/* Only interrupt boot if space is pressed */
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/* If a long serial cable is connected but */
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/* other end is dead, garbage will be read */
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#undef CONFIG_AUTOBOOT_DELAY_STR
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*
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* NAND-FLASH stuff
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*/
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define NAND_BIG_DELAY_US 25
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#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
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#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
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#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
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#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
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#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
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#define CONFIG_SYS_NAND_QUIET 1
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/*
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* PCI stuff
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
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#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
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#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
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#define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */
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/*
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* IDE/ATA stuff
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*/
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
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/* max. 1 drives per IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
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#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* FLASH organization
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*/
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#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
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#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */
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#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */
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/*
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* The following defines are added for buggy IOP480 byte interface.
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* All other boards should use the standard values (CPCI405 etc.)
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*/
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#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
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#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
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#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
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#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
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/*
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* Environment Variable setup
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*/
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#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */
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#define CONFIG_ENV_SIZE 0x700
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/*
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* I2C EEPROM (24WC16) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
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#define CONFIG_SYS_EEPROM_WREN 1
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/* 24WC16 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */
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/* 16 byte page write mode using */
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/* last 4 bits of the address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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/*
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* External Bus Controller (EBC) Setup
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*/
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#define CAN0_BA 0xF0000000 /* CAN0 Base Address */
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#define CAN1_BA 0xF0000100 /* CAN1 Base Address */
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#define DUART0_BA 0xF0000400 /* DUART Base Address */
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#define DUART1_BA 0xF0000408 /* DUART Base Address */
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#define RTC_BA 0xF0000500 /* RTC Base Address */
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#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
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#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
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/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
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/* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
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#define CONFIG_SYS_EBC_PB0AP 0x92015480
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/* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
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#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
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/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB1AP 0x92015480
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/* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
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#define CONFIG_SYS_EBC_PB1CR 0xF4018000
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/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
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/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CONFIG_SYS_EBC_PB2AP 0x010053C0
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/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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#define CONFIG_SYS_EBC_PB2CR 0xF0018000
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/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
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/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CONFIG_SYS_EBC_PB3AP 0x010053C0
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/* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
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#define CONFIG_SYS_EBC_PB3CR 0xF011A000
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/*
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* FPGA stuff
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*/
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#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
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/* FPGA internal regs */
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#define CONFIG_SYS_FPGA_CTRL 0x000
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/* FPGA Control Reg */
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#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
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#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
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#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
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#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
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#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
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/* FPGA program pin configuration */
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#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
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#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
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#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
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#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
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#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
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/*
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
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#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Definitions for GPIO setup (PPC405EP specific)
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*
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* GPIO0[0] - External Bus Controller BLAST output
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* GPIO0[1-9] - Instruction trace outputs -> GPIO
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* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
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* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
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* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
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* GPIO0[24-27] - UART0 control signal inputs/outputs
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* GPIO0[28-29] - UART1 data signal input/output
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* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
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*/
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#define CONFIG_SYS_GPIO0_OSRL 0x00000550
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#define CONFIG_SYS_GPIO0_OSRH 0x00000110
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#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
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#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
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#define CONFIG_SYS_GPIO0_TSRL 0x00000000
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#define CONFIG_SYS_GPIO0_TSRH 0x00000000
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#define CONFIG_SYS_GPIO0_TCR 0x77FE0014
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#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
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#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*
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* Default speed selection (cpu_plb_opb_ebc) in MHz.
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* This value will be set if iic boot eprom is disabled.
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*/
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#if 1
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#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
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#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
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#endif
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#if 0
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#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
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#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
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#endif
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#if 0
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#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
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#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
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#endif
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/*
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* PCI OHCI controller
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*/
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_PCI_OHCI 1
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#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
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#define CONFIG_USB_STORAGE 1
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/*
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* UBI
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*/
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#define CONFIG_CMD_UBI
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#define CONFIG_RBTREE
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_LZO
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#endif /* __CONFIG_H */
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