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ppc4xx: Use common NS16550 driver for PPC4xx UART

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This patch removes the PPC4xx UART driver. Instead the common NS16550
driver is used, since all PPC4xx SoC's use this peripheral device.

The file 4xx_uart.c now only implements the UART clock calculation
function which also sets the SoC internal UART divisors.

All PPC4xx board config headers are changed to use this common NS16550
driver now.

Tested on these boards:
acadia, canyonlands, katmai, kilauea, sequoia, zeus

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2010-09-20 16:05:31 +02:00
parent afabb498b7
commit 550650ddd0
107 changed files with 607 additions and 831 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

835
arch/powerpc/cpu/ppc4xx/4xx_uart.c
View file

@ -2,6 +2,9 @@
* (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -51,14 +54,6 @@
#include <watchdog.h>
#include <asm/ppc4xx.h>
#ifdef CONFIG_SERIAL_MULTI
#include <serial.h>
#endif
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
#include <malloc.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
@ -66,24 +61,6 @@ DECLARE_GLOBAL_DATA_PTR;
defined(CONFIG_405EX) || defined(CONFIG_440)
#if defined(CONFIG_440)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400)
#else
#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000200)
#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
#define UART3_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
#endif
#if defined(CONFIG_440GP)
#define CR0_MASK 0x3fff0000
@ -116,16 +93,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define MTREG(a, d) mtsdr(a, d)
#endif /* #if defined(CONFIG_440GP) */
#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
#define UCR0_MASK 0x0000007f
#define UCR1_MASK 0x00007f00
#define UCR0_UDIV_POS 0
#define UCR1_UDIV_POS 8
#define UDIV_MAX 127
#elif defined(CONFIG_405EX)
#define UART0_BASE 0xef600200
#define UART1_BASE 0xef600300
#define MFREG(a, d) mfsdr(a, d)
#define MTREG(a, d) mtsdr(a, d)
#define CR0_MASK 0x000000ff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
@ -133,223 +108,164 @@ DECLARE_GLOBAL_DATA_PTR;
#define UART0_SDR SDR0_UART0
#define UART1_SDR SDR0_UART1
#else /* CONFIG_405GP || CONFIG_405CR */
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
#define CR0_MASK 0x00001fff
#define CR0_EXTCLK_ENA 0x000000c0
#define CR0_UDIV_POS 1
#define UDIV_MAX 32
#endif
/* using serial port 0 or 1 as U-Boot console ? */
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
#endif
#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
#error "External serial clock not supported on AMCC PPC405EP!"
#endif
#define UART_RBR 0x00
#define UART_THR 0x00
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
#define UART_DLL 0x00
#define UART_DLM 0x01
/*-----------------------------------------------------------------------------+
| Line Status Register.
+-----------------------------------------------------------------------------*/
#define asyncLSRDataReady1 0x01
#define asyncLSROverrunError1 0x02
#define asyncLSRParityError1 0x04
#define asyncLSRFramingError1 0x08
#define asyncLSRBreakInterrupt1 0x10
#define asyncLSRTxHoldEmpty1 0x20
#define asyncLSRTxShiftEmpty1 0x40
#define asyncLSRRxFifoError1 0x80
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
/*-----------------------------------------------------------------------------+
| Fifo
+-----------------------------------------------------------------------------*/
typedef struct {
char *rx_buffer;
ulong rx_put;
ulong rx_get;
} serial_buffer_t;
volatile static serial_buffer_t buf_info;
#endif
static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
{
PPC4xx_SYS_INFO sys_info;
u8 val;
get_sys_info(&sys_info);
/* Correct UART frequency in bd-info struct now that
* the UART divisor is available
*/
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
#else
gd->uart_clk = sys_info.freqUART / udiv;
#endif
out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */
out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */
out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */
out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */
val = in_8((u8 *)base + UART_LSR); /* clear line status */
val = in_8((u8 *)base + UART_RBR); /* read receive buffer */
out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */
out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */
}
#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
!defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
static void serial_divs (int baudrate, unsigned long *pudiv,
unsigned short *pbdiv)
#if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \
defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
/*
* For some SoC's, the cpu clock is on divider chain A, UART on
* divider chain B ... so cpu clock is irrelevant. Get the
* "optimized" values that are subject to the 1/2 opb clock
* constraint.
*/
static u16 serial_bdiv(int baudrate, u32 *udiv)
{
sys_info_t sysinfo;
unsigned long div; /* total divisor udiv * bdiv */
unsigned long umin; /* minimum udiv */
unsigned short diff; /* smallest diff */
unsigned long udiv; /* best udiv */
unsigned short idiff; /* current diff */
unsigned short ibdiv; /* current bdiv */
unsigned long i;
unsigned long est; /* current estimate */
u32 div; /* total divisor udiv * bdiv */
u32 umin; /* minimum udiv */
u16 diff; /* smallest diff */
u16 idiff; /* current diff */
u16 ibdiv; /* current bdiv */
u32 i;
u32 est; /* current estimate */
u32 max;
#if defined(CONFIG_405EZ)
u32 cpr_pllc;
u32 plloutb;
u32 reg;
#endif
get_sys_info(&sysinfo);
udiv = 32; /* Assume lowest possible serial clk */
div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
diff = 32; /* highest possible */
/* i is the test udiv value -- start with the largest
* possible (32) to minimize serial clock and constrain
* search to umin.
*/
for (i = 32; i > umin; i--) {
ibdiv = div / i;
est = i * ibdiv;
idiff = (est > div) ? (est-div) : (div-est);
if (idiff == 0) {
udiv = i;
break; /* can't do better */
} else if (idiff < diff) {
udiv = i; /* best so far */
diff = idiff; /* update lowest diff*/
}
}
*pudiv = udiv;
*pbdiv = div / udiv;
}
#elif defined(CONFIG_405EZ)
static void serial_divs (int baudrate, unsigned long *pudiv,
unsigned short *pbdiv)
{
sys_info_t sysinfo;
unsigned long div; /* total divisor udiv * bdiv */
unsigned long umin; /* minimum udiv */
unsigned short diff; /* smallest diff */
unsigned long udiv; /* best udiv */
unsigned short idiff; /* current diff */
unsigned short ibdiv; /* current bdiv */
unsigned long i;
unsigned long est; /* current estimate */
unsigned long plloutb;
unsigned long cpr_pllc;
u32 reg;
#if defined(CONFIG_405EZ)
/* check the pll feedback source */
mfcpr(CPR0_PLLC, cpr_pllc);
get_sys_info(&sysinfo);
plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
udiv = 256; /* Assume lowest possible serial clk */
div = plloutb / (16 * baudrate); /* total divisor */
umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
diff = 256; /* highest possible */
max = 256; /* highest possible */
#else /* 405EZ */
div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
max = 32; /* highest possible */
#endif /* 405EZ */
/* i is the test udiv value -- start with the largest
* possible (256) to minimize serial clock and constrain
*udiv = diff = max;
/*
* i is the test udiv value -- start with the largest
* possible (max) to minimize serial clock and constrain
* search to umin.
*/
for (i = 256; i > umin; i--) {
for (i = max; i > umin; i--) {
ibdiv = div / i;
est = i * ibdiv;
idiff = (est > div) ? (est-div) : (div-est);
idiff = (est > div) ? (est - div) : (div - est);
if (idiff == 0) {
udiv = i;
break; /* can't do better */
*udiv = i;
break; /* can't do better */
} else if (idiff < diff) {
udiv = i; /* best so far */
diff = idiff; /* update lowest diff*/
*udiv = i; /* best so far */
diff = idiff; /* update lowest diff*/
}
}
*pudiv = udiv;
#if defined(CONFIG_405EZ)
mfcpr(CPR0_PERD0, reg);
reg &= ~0x0000ffff;
reg |= ((udiv - 0) << 8) | (udiv - 0);
reg |= ((*udiv - 0) << 8) | (*udiv - 0);
mtcpr(CPR0_PERD0, reg);
*pbdiv = div / udiv;
}
#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
/*
* Minimal serial functions needed to use one of the SMC ports
* as serial console interface.
*/
#if defined(CONFIG_440)
int serial_init_dev(unsigned long base)
{
unsigned long reg;
unsigned long udiv;
unsigned short bdiv;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
unsigned long tmp;
#endif
return div / *udiv;
}
#endif /* #if (defined(CONFIG_405EP) ... */
/*
* This function returns the UART clock used by the common
* NS16550 driver. Additionally the SoC internal divisors for
* optimal UART baudrate are configured.
*/
int get_serial_clock(void)
{
u32 clk;
u32 udiv;
#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || defined(CONFIG_405GP)
u32 tmp;
#endif
#if !defined(CONFIG_405EZ)
u32 reg;
#endif
#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
PPC4xx_SYS_INFO sys_info;
#endif
/*
* Programming of the internal divisors is SoC specific.
* Let's handle this in some #ifdef's for the SoC's.
*/
#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
tmp = 0;
reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
udiv = 1;
reg |= CR0_EXTCLK_ENA;
#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
clk = gd->cpu_clk;
#ifdef CONFIG_SYS_405_UART_ERRATA_59
udiv = 31; /* Errata 59: stuck at 31 */
#else /* CONFIG_SYS_405_UART_ERRATA_59 */
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
#endif /* CONFIG_SYS_405_UART_ERRATA_59 */
#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
mtdcr (CPC0_CR0, reg);
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
#else
clk = CONFIG_SYS_BASE_BAUD * 16;
#endif
#endif /* CONFIG_405CR */
#if defined(CONFIG_405EP)
reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */
reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */
mtdcr(CPC0_UCR, reg);
clk = CONFIG_SYS_BASE_BAUD * 16;
#endif /* CONFIG_405EP */
#if defined(CONFIG_405EX) || defined(CONFIG_440)
MFREG(UART0_SDR, reg);
reg &= ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
/* For 440, the cpu clock is on divider chain A, UART on divider
* chain B ... so cpu clock is irrelevant. Get the "optimized"
* values that are subject to the 1/2 opb clock constraint
*/
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
@ -367,514 +283,23 @@ int serial_init_dev(unsigned long base)
#if defined(UART3_SDR)
MTREG(UART3_SDR, reg);
#endif
#endif /* CONFIG_405EX ... */
serial_init_common(base, udiv, bdiv);
return (0);
}
#else /* !defined(CONFIG_440) */
int serial_init_dev (unsigned long base)
{
unsigned long reg;
unsigned long tmp;
unsigned long clk;
unsigned long udiv;
unsigned short bdiv;
#ifdef CONFIG_405EX
clk = tmp = 0;
mfsdr(UART0_SDR, reg);
reg &= ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
serial_divs(gd->baudrate, &udiv, &bdiv);
#endif
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_405EZ)
clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
#endif /* CONFIG_405EZ */
/*
* Configure input clock to baudrate generator for all
* available serial ports here
* Correct UART frequency in bd-info struct now that
* the UART divisor is available
*/
mtsdr(UART0_SDR, reg);
#if defined(UART1_SDR)
mtsdr(UART1_SDR, reg);
#endif
#elif defined(CONFIG_405EZ)
serial_divs(gd->baudrate, &udiv, &bdiv);
clk = tmp = reg = 0;
#else
#ifdef CONFIG_405EP
reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
mtdcr (CPC0_UCR, reg);
#else /* CONFIG_405EP */
reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
udiv = 1;
reg |= CR0_EXTCLK_ENA;
gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
#else
clk = gd->cpu_clk;
#ifdef CONFIG_SYS_405_UART_ERRATA_59
udiv = 31; /* Errata 59: stuck at 31 */
#else
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
#endif
#endif
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
mtdcr (CPC0_CR0, reg);
#endif /* CONFIG_405EP */
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
#endif /* CONFIG_405EX */
serial_init_common(base, udiv, bdiv);
return (0);
}
#endif /* if defined(CONFIG_440) */
void serial_setbrg_dev(unsigned long base)
{
serial_init_dev(base);
}
void serial_putc_dev(unsigned long base, const char c)
{
int i;
if (c == '\n')
serial_putc_dev(base, '\r');
/* check THRE bit, wait for transmiter available */
for (i = 1; i < 3500; i++) {
if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20)
break;
udelay (100);
}
out_8((u8 *)base + UART_THR, c); /* put character out */
}
void serial_puts_dev (unsigned long base, const char *s)
{
while (*s)
serial_putc_dev (base, *s++);
}
int serial_getc_dev (unsigned long base)
{
unsigned char status = 0;
while (1) {
#if defined(CONFIG_HW_WATCHDOG)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
#endif /* CONFIG_HW_WATCHDOG */
status = in_8((u8 *)base + UART_LSR);
if ((status & asyncLSRDataReady1) != 0x0)
break;
if ((status & ( asyncLSRFramingError1 |
asyncLSROverrunError1 |
asyncLSRParityError1 |
asyncLSRBreakInterrupt1 )) != 0) {
out_8((u8 *)base + UART_LSR,
asyncLSRFramingError1 |
asyncLSROverrunError1 |
asyncLSRParityError1 |
asyncLSRBreakInterrupt1);
}
}
return (0x000000ff & (int) in_8((u8 *)base));
}
int serial_tstc_dev (unsigned long base)
{
unsigned char status;
status = in_8((u8 *)base + UART_LSR);
if ((status & asyncLSRDataReady1) != 0x0)
return (1);
if ((status & ( asyncLSRFramingError1 |
asyncLSROverrunError1 |
asyncLSRParityError1 |
asyncLSRBreakInterrupt1 )) != 0) {
out_8((u8 *)base + UART_LSR,
asyncLSRFramingError1 |
asyncLSROverrunError1 |
asyncLSRParityError1 |
asyncLSRBreakInterrupt1);
}
return 0;
}
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
void serial_isr (void *arg)
{
int space;
int c;
const int rx_get = buf_info.rx_get;
int rx_put = buf_info.rx_put;
if (rx_get <= rx_put)
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
else
space = rx_get - rx_put;
while (serial_tstc_dev (ACTING_UART0_BASE)) {
c = serial_getc_dev (ACTING_UART0_BASE);
if (space) {
buf_info.rx_buffer[rx_put++] = c;
space--;
}
if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
rx_put = 0;
if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
/* Stop flow by setting RTS inactive */
out_8((u8 *)ACTING_UART0_BASE + UART_MCR,
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) &
(0xFF ^ 0x02));
}
}
buf_info.rx_put = rx_put;
}
void serial_buffered_init (void)
{
serial_puts ("Switching to interrupt driven serial input mode.\n");
buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
buf_info.rx_put = 0;
buf_info.rx_get = 0;
if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)
serial_puts ("Check CTS signal present on serial port: OK.\n");
else
serial_puts ("WARNING: CTS signal not present on serial port.\n");
irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
serial_isr /*interrupt_handler_t *handler */ ,
(void *) &buf_info /*void *arg */ );
/* Enable "RX Data Available" Interrupt on UART */
out_8(ACTING_UART0_BASE + UART_IER, 0x01);
/* Set DTR active */
out_8(ACTING_UART0_BASE + UART_MCR,
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01);
/* Start flow by setting RTS active */
out_8(ACTING_UART0_BASE + UART_MCR,
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
}
void serial_buffered_putc (const char c)
{
/* Wait for CTS */
#if defined(CONFIG_HW_WATCHDOG)
while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10))
WATCHDOG_RESET ();
#else
while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10));
#endif
serial_putc (c);
}
void serial_buffered_puts (const char *s)
{
serial_puts (s);
}
int serial_buffered_getc (void)
{
int space;
int c;
int rx_get = buf_info.rx_get;
int rx_put;
#if defined(CONFIG_HW_WATCHDOG)
while (rx_get == buf_info.rx_put)
WATCHDOG_RESET ();
#else
while (rx_get == buf_info.rx_put);
#endif
c = buf_info.rx_buffer[rx_get++];
if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
rx_get = 0;
buf_info.rx_get = rx_get;
rx_put = buf_info.rx_put;
if (rx_get <= rx_put)
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
else
space = rx_get - rx_put;
if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
/* Start flow by setting RTS active */
out_8(ACTING_UART0_BASE + UART_MCR,
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
}
return c;
}
int serial_buffered_tstc (void)
{
return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
}
#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
#if defined(CONFIG_CMD_KGDB)
/*
AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
number 0 or number 1
- if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
configuration has been already done
- if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
*/
#if (CONFIG_KGDB_SER_INDEX & 2)
void kgdb_serial_init (void)
{
u8 val;
u16 br_reg;
get_clocks ();
br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
5) / 10;
/*
* Init onboard 16550 UART
*/
out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */
val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
}
void putDebugChar (const char c)
{
if (c == '\n')
serial_putc ('\r');
out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */
/* check THRE bit, wait for transfer done */
while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
}
void putDebugStr (const char *s)
{
while (*s)
serial_putc (*s++);
}
int getDebugChar (void)
{
unsigned char status = 0;
while (1) {
status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR);
if ((status & asyncLSRDataReady1) != 0x0)
break;
if ((status & (asyncLSRFramingError1 |
asyncLSROverrunError1 |
asyncLSRParityError1 |
asyncLSRBreakInterrupt1 )) != 0) {
out_8((u8 *)ACTING_UART1_BASE + UART_LSR,
asyncLSRFramingError1 |
asyncLSROverrunError1 |
asyncLSRParityError1 |
asyncLSRBreakInterrupt1);
}
}
return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE));
}
void kgdb_interruptible (int yes)
{
return;
}
#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
void kgdb_serial_init (void)
{
serial_printf ("[on serial] ");
}
void putDebugChar (int c)
{
serial_putc (c);
}
void putDebugStr (const char *str)
{
serial_puts (str);
}
int getDebugChar (void)
{
return serial_getc ();
}
void kgdb_interruptible (int yes)
{
return;
}
#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
get_sys_info(&sys_info);
gd->uart_clk = sys_info.freqUART / udiv;
#endif
#if defined(CONFIG_SERIAL_MULTI)
int serial0_init(void)
{
return (serial_init_dev(UART0_BASE));
return clk;
}
int serial1_init(void)
{
return (serial_init_dev(UART1_BASE));
}
void serial0_setbrg (void)
{
serial_setbrg_dev(UART0_BASE);
}
void serial1_setbrg (void)
{
serial_setbrg_dev(UART1_BASE);
}
void serial0_putc(const char c)
{
serial_putc_dev(UART0_BASE,c);
}
void serial1_putc(const char c)
{
serial_putc_dev(UART1_BASE, c);
}
void serial0_puts(const char *s)
{
serial_puts_dev(UART0_BASE, s);
}
void serial1_puts(const char *s)
{
serial_puts_dev(UART1_BASE, s);
}
int serial0_getc(void)
{
return(serial_getc_dev(UART0_BASE));
}
int serial1_getc(void)
{
return(serial_getc_dev(UART1_BASE));
}
int serial0_tstc(void)
{
return (serial_tstc_dev(UART0_BASE));
}
int serial1_tstc(void)
{
return (serial_tstc_dev(UART1_BASE));
}
struct serial_device serial0_device =
{
"serial0",
"UART0",
serial0_init,
NULL,
serial0_setbrg,
serial0_getc,
serial0_tstc,
serial0_putc,
serial0_puts,
};
struct serial_device serial1_device =
{
"serial1",
"UART1",
serial1_init,
NULL,
serial1_setbrg,
serial1_getc,
serial1_tstc,
serial1_putc,
serial1_puts,
};
#else
/*
* Wrapper functions
*/
int serial_init(void)
{
return serial_init_dev(ACTING_UART0_BASE);
}
void serial_setbrg(void)
{
serial_setbrg_dev(ACTING_UART0_BASE);
}
void serial_putc(const char c)
{
serial_putc_dev(ACTING_UART0_BASE, c);
}
void serial_puts(const char *s)
{
serial_puts_dev(ACTING_UART0_BASE, s);
}
int serial_getc(void)
{
return serial_getc_dev(ACTING_UART0_BASE);
}
int serial_tstc(void)
{
return serial_tstc_dev(ACTING_UART0_BASE);
}
#endif /* CONFIG_SERIAL_MULTI */
#endif /* CONFIG_405GP || CONFIG_405CR */

7
arch/powerpc/include/asm/ppc405cr.h
View file

@ -24,7 +24,12 @@
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
/* Memory mapped register */
#define GPIO0_BASE 0xef600700
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
/* DCR's */
#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */

7
arch/powerpc/include/asm/ppc405ep.h
View file

@ -24,7 +24,12 @@
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
/* Memory mapped register */
#define GPIO0_BASE 0xef600700
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
/* DCR */
#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */

7
arch/powerpc/include/asm/ppc405ex.h
View file

@ -26,7 +26,12 @@
#define CONFIG_NAND_NDFC
/* Memory mapped register */
#define GPIO0_BASE 0xef600800
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
/* SDR */
#define SDR0_SDCS0 0x0060

9
arch/powerpc/include/asm/ppc405ez.h
View file

@ -24,8 +24,13 @@
#define CONFIG_NAND_NDFC
/* Memory mapped register */
#define GPIO0_BASE 0xef600700
#define GPIO1_BASE 0xef600800
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
/* DCR register */
#define OCM0_PLBCR1 0x0020 /* OCM PLB3 Bank 1 Config */

7
arch/powerpc/include/asm/ppc405gp.h
View file

@ -24,7 +24,12 @@
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
/* Memory mapped register */
#define GPIO0_BASE 0xef600700
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
/* DCR's */
#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */

14
arch/powerpc/include/asm/ppc440ep_gr.h
View file

@ -28,9 +28,19 @@
/*
* Some SoC specific registers (not common for all 440 SoC's)
*/
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000B00)
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000C00)
/* Memory mapped registers */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
/* SDR's */
#define SDR0_PCI0 0x0300
#define SDR0_SDSTP2 0x4001
#define SDR0_SDSTP3 0x4003

12
arch/powerpc/include/asm/ppc440epx_grx.h
View file

@ -30,9 +30,15 @@
*/
/* Memory mapped registers */
#define SPI0_MODE 0xef600090
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000B00)
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000C00)
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
#define SPI0_MODE (CONFIG_SYS_PERIPHERAL_BASE + 0x0090)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
/* DCR */
#define CPM0_ER 0x00b0

9
arch/powerpc/include/asm/ppc440gp.h
View file

@ -26,7 +26,14 @@
/*
* Some SoC specific registers (not common for all 440 SoC's)
*/
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
/* Memory mapped register */
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
#define SDR0_PCI0 0x0300

10
arch/powerpc/include/asm/ppc440gx.h
View file

@ -26,8 +26,16 @@
/*
* Some SoC specific registers (not common for all 440 SoC's)
*/
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
/* Memory mapped register */
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
/* SDR's */
#define SDR0_PCI0 0x0300
#define SDR0_SDSTP2 0x4001

10
arch/powerpc/include/asm/ppc440sp.h
View file

@ -26,8 +26,16 @@
/*
* Some SoC specific registers (not common for all 440 SoC's)
*/
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
/* Memory mapped register */
#define CONFIG_SYS_PERIPHERAL_BASE 0xf0000000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
/* SDR's */
#define SDR0_PCI0 0x0300
#define SDR0_SDSTP2 0x0022
#define SDR0_SDSTP3 0x0023

9
arch/powerpc/include/asm/ppc440spe.h
View file

@ -27,8 +27,15 @@
* Some SoC specific registers (not common for all 440 SoC's)
*/
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
/* Memory mapped register */
#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
/* SDR's */
#define SDR0_PCI0 0x0300
#define SDR0_SDSTP2 0x0022
#define SDR0_SDSTP3 0x0023

12
arch/powerpc/include/asm/ppc460ex_gt.h
View file

@ -29,8 +29,16 @@
* Some SoC specific registers
*/
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000B00)
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000C00)
/* Memory mapped registers */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
/* DCR */
#define AHB_TOP 0x00a4

8
arch/powerpc/include/asm/ppc460sx.h
View file

@ -23,7 +23,13 @@
#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
/* Memory mapped registers */
#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
#define SDR0_SRST0_DMC 0x00200000

16
arch/powerpc/include/asm/ppc4xx.h
View file

@ -202,6 +202,22 @@
#define GPT0_DCT0 0x00000110
#define GPT0_DCIS 0x0000011C
#if 0 // test-only
/*
* All PPC4xx share the same NS16550 UART(s). Only base addresses
* may differ. We define here the integration of the common NS16550
* driver for all PPC4xx SoC's. The board config header must specify
* on which UART the console should be located via CONFIG_CONS_INDEX.
*/
#if 0 /* test-only */
#define CONFIG_SERIAL_MULTI
#endif
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#endif
#if defined(CONFIG_440)
#include <asm/ppc440.h>
#else

1
board/amcc/ebony/init.S
View file

@ -23,6 +23,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/amcc/katmai/init.S
View file

@ -26,6 +26,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/amcc/luan/init.S
View file

@ -26,6 +26,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/amcc/ocotea/init.S
View file

@ -23,6 +23,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/amcc/redwood/init.S
View file

@ -24,6 +24,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/amcc/taishan/init.S
View file

@ -24,6 +24,7 @@
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/amcc/yucca/init.S
View file

@ -26,6 +26,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

6
board/esd/pmc440/pmc440.c
View file

@ -68,7 +68,7 @@ struct serial_device *default_serial_console(void)
*/
mfsdr(SDR0_PINSTP, val);
if (((val & 0xf0000000) >> 29) != 7)
return &serial1_device;
return &eserial2_device;
ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
if (!(scratchreg & 0x80)) {
@ -90,9 +90,9 @@ struct serial_device *default_serial_console(void)
}
if (scratchreg & 0x01)
return &serial1_device;
return &eserial2_device;
else
return &serial0_device;
return &eserial1_device;
}
int board_early_init_f(void)

1
board/mosaixtech/icon/init.S
View file

@ -24,6 +24,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
#include <asm/ppc4xx.h>
/*
* TLB TABLE

1
board/prodrive/alpr/init.S
View file

@ -24,6 +24,7 @@
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/prodrive/p3p440/init.S
View file

@ -26,6 +26,7 @@
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/sandburst/karef/init.S
View file

@ -26,6 +26,7 @@
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/sandburst/metrobox/init.S
View file

@ -24,6 +24,7 @@
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE

1
board/xes/xpedite1000/init.S
View file

@ -23,6 +23,7 @@
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
#include <asm/ppc4xx.h>
/*
* TLB TABLE

10
common/serial.c
View file

@ -38,8 +38,7 @@ struct serial_device *__default_serial_console (void)
#elif defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
#elif defined(CONFIG_4xx) \
|| defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \
|| defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \
|| defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520)
@ -127,13 +126,6 @@ void serial_initialize (void)
serial_register (&serial_scc_device);
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
|| defined(CONFIG_MPC5xxx)
serial_register(&serial0_device);
serial_register(&serial1_device);
#endif
#if defined(CONFIG_SYS_NS16550_SERIAL)
#if defined(CONFIG_SYS_NS16550_COM1)
serial_register(&eserial1_device);

1
include/common.h
View file

@ -535,6 +535,7 @@ ulong get_PERCLK2(void);
ulong get_PERCLK3(void);
#endif
ulong get_bus_freq (ulong);
int get_serial_clock(void);
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;

6
include/configs/APC405.h
View file

@ -176,6 +176,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
/* The following table includes the supported baudrates */

6
include/configs/AR405.h
View file

@ -127,6 +127,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
/* The following table includes the supported baudrates */

7
include/configs/ASH405.h
View file

@ -124,9 +124,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

6
include/configs/CANBT.h
View file

@ -100,6 +100,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
/* The following table includes the supported baudrates */

6
include/configs/CATcenter.h
View file

@ -86,7 +86,11 @@
# error "* External frequency (SysClk) not defined! *"
#endif
#define CONFIG_UART1_CONSOLE 1 /* Use second UART */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */

7
include/configs/CMS700.h
View file

@ -122,9 +122,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

7
include/configs/CPCI2DP.h
View file

@ -111,9 +111,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

6
include/configs/CPCI405.h
View file

@ -125,6 +125,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

6
include/configs/CPCI4052.h
View file

@ -134,6 +134,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

6
include/configs/CPCI405AB.h
View file

@ -133,6 +133,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

6
include/configs/CPCI405DT.h
View file

@ -135,6 +135,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

6
include/configs/CPCIISER4.h
View file

@ -110,6 +110,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */
/* The following table includes the supported baudrates */

6
include/configs/CRAYL1.h
View file

@ -47,6 +47,12 @@
#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
#define CONFIG_NET_MULTI
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
* keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
#define CONFIG_PRAM 16

7
include/configs/DP405.h
View file

@ -97,9 +97,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

6
include/configs/DU405.h
View file

@ -109,6 +109,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
/* The following table includes the supported baudrates */

9
include/configs/DU440.h
View file

@ -64,9 +64,6 @@
#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
@ -86,10 +83,14 @@
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_UART1_CONSOLE
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

6
include/configs/ERIC.h
View file

@ -139,6 +139,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 14318180
/* The following table includes the supported baudrates */

7
include/configs/G2000.h
View file

@ -151,9 +151,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

7
include/configs/HH405.h
View file

@ -176,9 +176,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

7
include/configs/HUB405.h
View file

@ -118,9 +118,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

8
include/configs/JSE.h
View file

@ -95,9 +95,13 @@
#define CONFIG_ENV_OFFSET 0x00
#define CONFIG_ENV_SIZE 512
/* The JSE connects UART1 to the console tap connector. */
#define CONFIG_UART1_CONSOLE 1
#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* Set console baudrate to 9600 */
#define CONFIG_BAUDRATE 9600

6
include/configs/KAREF.h
View file

@ -59,7 +59,6 @@
#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
@ -91,6 +90,11 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 9600

6
include/configs/METROBOX.h
View file

@ -125,7 +125,6 @@
#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
@ -153,6 +152,11 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 9600

6
include/configs/MIP405.h
View file

@ -176,6 +176,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 916667

6
include/configs/OCRTC.h
View file

@ -105,6 +105,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

6
include/configs/ORSG.h
View file

@ -105,6 +105,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

6
include/configs/PCI405.h
View file

@ -110,6 +110,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

6
include/configs/PIP405.h
View file

@ -167,6 +167,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

7
include/configs/PLU405.h
View file

@ -135,9 +135,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

6
include/configs/PMC405.h
View file

@ -130,6 +130,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */
#define CONFIG_SYS_BASE_BAUD 806400

7
include/configs/PMC405DE.h
View file

@ -107,9 +107,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_UART1_CONSOLE
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

11
include/configs/PMC440.h
View file

@ -72,9 +72,6 @@
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
#define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
@ -95,10 +92,14 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_UART1_CONSOLE /* console on front panel */
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

6
include/configs/PPChameleonEVB.h
View file

@ -191,6 +191,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

7
include/configs/VOH405.h
View file

@ -133,9 +133,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

7
include/configs/VOM405.h
View file

@ -120,9 +120,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

6
include/configs/W7OLMC.h
View file

@ -125,6 +125,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD 384000

6
include/configs/W7OLMG.h
View file

@ -133,6 +133,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD 384000

7
include/configs/WUH405.h
View file

@ -122,9 +122,14 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \

7
include/configs/XPEDITE1000.h
View file

@ -54,7 +54,6 @@
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
@ -112,6 +111,12 @@ extern void out32(unsigned int, unsigned long);
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
#define CONFIG_BAUDRATE 115200

1
include/configs/acadia.h
View file

@ -89,6 +89,7 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SYS_BASE_BAUD 691200

8
include/configs/alpr.h
View file

@ -45,7 +45,6 @@
#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
@ -75,9 +74,14 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

6
include/configs/amcc-common.h
View file

@ -31,8 +31,12 @@
/*
* UART
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

6
include/configs/bamboo.h
View file

@ -62,8 +62,7 @@
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
/*Don't change either of these*/
#define CONFIG_SYS_USB_DEVICE 0x50000000
@ -85,9 +84,8 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
/*-----------------------------------------------------------------------
* NVRAM/RTC

1
include/configs/bubinga.h
View file

@ -123,6 +123,7 @@
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */

4
include/configs/canyonlands.h
View file

@ -114,8 +114,6 @@
#define CONFIG_SYS_SRAM_SIZE (256 << 10)
#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */
/*-----------------------------------------------------------------------
@ -130,7 +128,7 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
/*-----------------------------------------------------------------------
* Environment

6
include/configs/csb272.h
View file

@ -160,6 +160,12 @@
* UART configuration
*
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
#undef CONFIG_SYS_BASE_BAUD
#define CONFIG_BAUDRATE 38400 /* Default baud rate */

6
include/configs/csb472.h
View file

@ -159,6 +159,12 @@
* UART configuration
*
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_BAUDRATE 38400 /* Default baud rate */

1
include/configs/dlvision.h
View file

@ -97,6 +97,7 @@
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */

2
include/configs/ebony.h
View file

@ -61,7 +61,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
@ -81,6 +80,7 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */

7
include/configs/gdppc440etx.h
View file

@ -59,7 +59,6 @@
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripheral*/
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */
/*Don't change either of these*/
@ -80,8 +79,12 @@
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
#define CONFIG_UART1_CONSOLE
/*
* Environment

4
include/configs/hcu5.h
View file

@ -70,9 +70,6 @@
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
@ -94,7 +91,6 @@
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_BAUDRATE 115200
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_UART1_CONSOLE
/*-----------------------------------------------------------------------
* Environment

3
include/configs/icon.h
View file

@ -52,7 +52,6 @@
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */
#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
@ -106,7 +105,7 @@
/*
* Serial Port
*/
#undef CONFIG_UART1_CONSOLE
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
/*

4
include/configs/intip.h
View file

@ -96,8 +96,6 @@
#define CONFIG_SYS_SRAM_SIZE (256 << 10)
#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */
#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
/*
@ -113,7 +111,7 @@
/*
* Serial Port
*/
#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
/*
* Environment

3
include/configs/katmai.h
View file

@ -61,7 +61,6 @@
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
@ -105,7 +104,7 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_UART1_CONSOLE
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
/*-----------------------------------------------------------------------

4
include/configs/kilauea.h
View file

@ -57,7 +57,6 @@
#define CONFIG_SYS_FLASH_BASE 0xFC000000
#define CONFIG_SYS_NAND_ADDR 0xF8000000
#define CONFIG_SYS_FPGA_BASE 0xF0000000
#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
/*-----------------------------------------------------------------------
* Initial RAM & Stack Pointer Configuration Options
@ -115,8 +114,7 @@
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
/*-----------------------------------------------------------------------
* Environment

10
include/configs/korat.h
View file

@ -71,9 +71,6 @@
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
@ -93,11 +90,14 @@
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

4
include/configs/luan.h
View file

@ -58,8 +58,6 @@
#define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
#define CONFIG_SYS_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
@ -88,8 +86,8 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */
/*-----------------------------------------------------------------------
* Environment

10
include/configs/lwmon5.h
View file

@ -62,9 +62,6 @@
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
@ -106,11 +103,14 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

4
include/configs/makalu.h
View file

@ -55,7 +55,6 @@
*----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE 0xFC000000
#define CONFIG_SYS_FPGA_BASE 0xF0000000
#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
/*-----------------------------------------------------------------------
* Initial RAM & Stack Pointer Configuration Options
@ -112,9 +111,8 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no ext. clk */
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
/*-----------------------------------------------------------------------
* Environment

6
include/configs/neo.h
View file

@ -98,6 +98,12 @@
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */

5
include/configs/netstal-common.h
View file

@ -34,7 +34,12 @@
/*
* UART
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

2
include/configs/ocotea.h
View file

@ -58,7 +58,6 @@
*----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
@ -81,6 +80,7 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */

7
include/configs/p3p440.h
View file

@ -49,7 +49,6 @@
#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
@ -80,6 +79,12 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200

8
include/configs/pcs440ep.h
View file

@ -60,7 +60,6 @@
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
/*Don't change either of these*/
@ -80,11 +79,14 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

5
include/configs/quad100hd.h
View file

@ -105,6 +105,11 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200

6
include/configs/redwood.h
View file

@ -47,7 +47,6 @@
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
@ -77,6 +76,11 @@
#define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */
#define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/

6
include/configs/sbc405.h
View file

@ -147,6 +147,12 @@
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200

5
include/configs/sc3.h
View file

@ -76,6 +76,11 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SERIAL_MULTI
#undef CONFIG_SERIAL_SOFTWARE_FIFO
/*

6
include/configs/sequoia.h
View file

@ -84,9 +84,6 @@
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
@ -105,9 +102,8 @@
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
/*
* Environment

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