mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
308520b8f2
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
217 lines
6.5 KiB
C
217 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015 Freescale Semiconductor
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* Copyright 2022 NXP
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*/
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#ifndef __LS1043ARDB_H__
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#define __LS1043ARDB_H__
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#include "ls1043a_common.h"
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/* Physical Memory Map */
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#ifndef CONFIG_SPL
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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/*
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* NOR Flash Definitions
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*/
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#define CFG_SYS_NOR_CSPR_EXT (0x0)
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#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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#define CFG_SYS_NOR_CSPR \
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(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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/* NOR Flash Timing Params */
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#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_TRHZ_80)
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#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
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FTIM0_NOR_TEADC(0x1) | \
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FTIM0_NOR_TAVDS(0x0) | \
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FTIM0_NOR_TEAHC(0xc))
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#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
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FTIM1_NOR_TRAD_NOR(0xb) | \
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FTIM1_NOR_TSEQRAD_NOR(0x9))
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#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0x8) | \
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FTIM2_NOR_TWP(0x10))
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#define CFG_SYS_NOR_FTIM3 0
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#define CFG_SYS_IFC_CCR 0x01000000
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#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
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#define CFG_SYS_WRITE_SWAPPED_DATA
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/*
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* NAND Flash Definitions
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*/
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#define CFG_SYS_NAND_BASE 0x7e800000
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#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
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#define CFG_SYS_NAND_CSPR_EXT (0x0)
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#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x7) | \
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FTIM0_NAND_TWH(0xa))
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#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0xe) | \
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FTIM1_NAND_TRP(0x18))
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#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
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FTIM2_NAND_TREH(0xa) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CFG_SYS_NAND_FTIM3 0x0
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#ifdef CONFIG_NAND_BOOT
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#define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
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#endif
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/*
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* CPLD
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*/
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#define CFG_SYS_CPLD_BASE 0x7fb00000
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#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
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#define CFG_SYS_CPLD_CSPR_EXT (0x0)
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#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
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#define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_NOR_MODE_AVD_NOR | \
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CSOR_NOR_TRHZ_80)
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/* CPLD Timing parameters for IFC GPCM */
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#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
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FTIM0_GPCM_TEADC(0xf) | \
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FTIM0_GPCM_TEAHC(0xf))
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#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0xff))
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#define CFG_SYS_CPLD_FTIM3 0x0
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/* IFC Timing Params */
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#ifdef CONFIG_TFABOOT
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
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#else
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#ifdef CONFIG_NAND_BOOT
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#else
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
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#endif
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#endif
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#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT
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#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR
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#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK
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#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR
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#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0
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#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1
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#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2
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#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3
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/*
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* Environment
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*/
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/* FMan */
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#ifndef SPL_NO_FMAN
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#define AQR105_IRQ_MASK 0x40000000
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define RGMII_PHY1_ADDR 0x1
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#define RGMII_PHY2_ADDR 0x2
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#define QSGMII_PORT1_PHY_ADDR 0x4
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#define QSGMII_PORT2_PHY_ADDR 0x5
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#define QSGMII_PORT3_PHY_ADDR 0x6
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#define QSGMII_PORT4_PHY_ADDR 0x7
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/* The AQR PHY model and MDIO address differ between board revisions */
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#define FM1_10GEC1_PHY_ADDR 0x1 /* AQR105 on boards up to v6.0 */
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#define AQR113C_PHY_ADDR 0x8 /* AQR113C on boards v7.0 and up */
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#endif
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#endif
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/* SATA */
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#ifndef SPL_NO_SATA
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#define SCSI_VEND_ID 0x1b4b
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#define SCSI_DEV_ID 0x9170
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#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
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#endif
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#include <asm/fsl_secure_boot.h>
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#endif /* __LS1043ARDB_H__ */
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