Sean Anderson b8bc120927 riscv: Add option to support RISC-V privileged spec 1.9 ... Some older processors (notably the Kendryte K210) use an older version of the RISC-V privileged specification. The primary changes between the old and new are in virtual memory, and in the merging of three separate counter enable CSRs. Using the new CSR on an old processor causes an illegal instruction exception. This patch adds an option to use the old CSRs instead of the new one. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2020-07-01 15:01:22 +08:00
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ax25	common: Drop net.h from common header	2020-05-18 17:33:31 -04:00
fu540	riscv: sifive: fu540: add SPL configuration	2020-06-04 09:44:09 +08:00
generic	common: Drop net.h from common header	2020-05-18 17:33:31 -04:00
cpu.c	riscv: Add option to support RISC-V privileged spec 1.9	2020-07-01 15:01:22 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: Clear pending interrupts before enabling IPIs	2020-07-01 15:01:21 +08:00
u-boot-spl.lds	riscv: Add _image_binary_end for SPL	2020-06-04 09:44:08 +08:00
u-boot.lds	riscv: Fix breakage caused by linker relaxation	2020-02-10 14:50:53 +08:00