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https://github.com/AsahiLinux/u-boot
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4909b89ec7
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
50 lines
1.1 KiB
Makefile
50 lines
1.1 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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# Copyright 2016-2018 NXP
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# Copyright 2014-2015, Freescale Semiconductor
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obj-y += cpu.o
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obj-y += lowlevel.o
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obj-y += soc.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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endif
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obj-$(CONFIG_SPL) += spl.o
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obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
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ifneq ($(CONFIG_FSL_LSCH3),)
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obj-y += fsl_lsch3_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
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else
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ifneq ($(CONFIG_FSL_LSCH2),)
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obj-y += fsl_lsch2_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
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endif
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endif
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ifneq ($(CONFIG_ARCH_LX2160A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS2080A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS1043A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
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obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
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obj-y += icid.o ls1043_ids.o
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endif
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ifneq ($(CONFIG_ARCH_LS1012A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS1046A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
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obj-y += icid.o ls1046_ids.o
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endif
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ifneq ($(CONFIG_ARCH_LS1088A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
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endif
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