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Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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ddr.c | ||
eth.c | ||
law.c | ||
Makefile | ||
pci.c | ||
t4qds.c | ||
t4qds.h | ||
t4240qds_qixis.h | ||
tlb.c |