mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
19b4040df0
This converts the following to Kconfig: CONFIG_HWCONFIG Signed-off-by: Tom Rini <trini@konsulko.com>
459 lines
14 KiB
C
459 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2020-2021 NXP
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/stringify.h>
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/*
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* T104x RDB board configuration file
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*/
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#include <asm/config_mpc85xx.h>
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#ifdef CONFIG_RAMBOOT_PBL
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#define RESET_VECTOR_OFFSET 0x27FFC
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#define BOOT_PAGE_OFFSET 0x27000
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#ifdef CONFIG_MTD_RAW_NAND
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#ifdef CONFIG_NXP_ESBC
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#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
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/*
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* HDR would be appended at end of image and copied to DDR along
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* with U-Boot image.
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*/
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#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
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CONFIG_U_BOOT_HDR_SIZE)
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#else
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#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
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#endif
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#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
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#define CFG_SYS_NAND_U_BOOT_START 0x30000000
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
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#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
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#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
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#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
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#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
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#endif
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#endif
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/* High Level Configuration Options */
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
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/*
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* For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence
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* Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address
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* (CFG_SYS_INIT_L3_VADDR) will be different.
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*/
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#define CFG_SYS_INIT_L3_VADDR 0xFFFC0000
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#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
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#define CFG_SYS_DCSRBAR 0xf0000000
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#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
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/*
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* DDR Setup
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*/
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#define CONFIG_VERY_BIG_RAM
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#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
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#define SPD_EEPROM_ADDRESS 0x51
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#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
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/*
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* IFC Definitions
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*/
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#define CFG_SYS_FLASH_BASE 0xe8000000
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#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
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#define CFG_SYS_NOR_CSPR_EXT (0xf)
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#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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/*
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* TDM Definition
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*/
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#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
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/* NOR Flash Timing Params */
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#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
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#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1A) |\
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0x0E) | \
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FTIM2_NOR_TWP(0x1c))
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#define CFG_SYS_NOR_FTIM3 0x0
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
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/* CPLD on IFC */
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#define CPLD_LBMAP_MASK 0x3F
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_OVERRIDE 0x40
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#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
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#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
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#define CPLD_LBMAP_RESET 0xFF
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#define CPLD_LBMAP_SHIFT 0x03
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#if defined(CONFIG_TARGET_T1042RDB_PI)
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#define CPLD_DIU_SEL_DFP 0x80
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#elif defined(CONFIG_TARGET_T1042D4RDB)
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#define CPLD_DIU_SEL_DFP 0xc0
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#endif
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#if defined(CONFIG_TARGET_T1040D4RDB)
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#define CPLD_INT_MASK_ALL 0xFF
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#define CPLD_INT_MASK_THERM 0x80
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#define CPLD_INT_MASK_DVI_DFP 0x40
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#define CPLD_INT_MASK_QSGMII1 0x20
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#define CPLD_INT_MASK_QSGMII2 0x10
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#define CPLD_INT_MASK_SGMI1 0x08
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#define CPLD_INT_MASK_SGMI2 0x04
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#define CPLD_INT_MASK_TDMR1 0x02
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#define CPLD_INT_MASK_TDMR2 0x01
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#endif
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#define CFG_SYS_CPLD_BASE 0xffdf0000
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#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
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#define CFG_SYS_CSPR2_EXT (0xf)
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#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
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#define CFG_SYS_CSOR2 0x0
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/* CPLD Timing parameters for IFC CS2 */
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#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e))
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#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
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FTIM1_GPCM_TRAD(0x1f))
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#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
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FTIM2_GPCM_TCH(0x8) | \
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FTIM2_GPCM_TWP(0x1f))
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#define CFG_SYS_CS2_FTIM3 0x0
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/* NAND Flash on IFC */
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#define CFG_SYS_NAND_BASE 0xff800000
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#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
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#define CFG_SYS_NAND_CSPR_EXT (0xf)
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#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
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| CSPR_MSEL_NAND /* MSEL = NAND */ \
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| CSPR_V)
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#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
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| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
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| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
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| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
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/* ONFI NAND Flash mode0 Timing Params */
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#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x07) | \
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FTIM0_NAND_TWH(0x0a))
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#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0x0e) | \
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FTIM1_NAND_TRP(0x18))
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#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
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FTIM2_NAND_TREH(0x0a) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CFG_SYS_NAND_FTIM3 0x0
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#if defined(CONFIG_MTD_RAW_NAND)
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#else
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
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#endif
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/* define to use L1 as initial stack */
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#define CONFIG_L1_INIT_RAM
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#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
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/* The assembler doesn't like typecast */
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#define CFG_SYS_INIT_RAM_ADDR_PHYS \
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((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#define CFG_SYS_INIT_RAM_SIZE 0x00004000
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#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
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#define CFG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
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#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
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#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
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#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR 0x70
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#define I2C_MUX_CH_DEFAULT 0x8
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#if defined(CONFIG_TARGET_T1042RDB_PI) || \
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defined(CONFIG_TARGET_T1040D4RDB) || \
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defined(CONFIG_TARGET_T1042D4RDB)
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/*
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* RTC configuration
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*/
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#define RTC
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#define CONFIG_RTC_DS1337 1
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#define CFG_SYS_I2C_RTC_ADDR 0x68
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/*DVI encoder*/
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#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
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#endif
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/*
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* eSPI - Enhanced SPI
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*/
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#ifdef CONFIG_PCI
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */
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#ifdef CONFIG_PCIE1
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#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
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#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
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#endif
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/* controller 2, Slot 2, tgtid 2, Base address 201000 */
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#ifdef CONFIG_PCIE2
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#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
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#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
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#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
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#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
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#endif
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/* controller 3, Slot 1, tgtid 1, Base address 202000 */
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#ifdef CONFIG_PCIE3
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#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
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#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
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#endif
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/* controller 4, Base address 203000 */
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#ifdef CONFIG_PCIE4
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#define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000
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#define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
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#endif
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#endif /* CONFIG_PCI */
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/*
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* USB
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*/
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#ifdef CONFIG_MMC
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#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
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#endif
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/* Qman/Bman */
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#ifndef CONFIG_NOBQFMAN
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#define CFG_SYS_BMAN_NUM_PORTALS 10
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#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
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#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
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#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
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#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
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#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
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#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
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#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
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#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
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CFG_SYS_BMAN_CENA_SIZE)
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#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
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#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
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#define CFG_SYS_QMAN_NUM_PORTALS 10
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#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
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#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
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#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
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#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
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#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
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#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
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CFG_SYS_QMAN_CENA_SIZE)
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#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
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#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
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#endif /* CONFIG_NOBQFMAN */
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#ifdef CONFIG_FMAN_ENET
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#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
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#define CFG_SYS_SGMII1_PHY_ADDR 0x03
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#elif defined(CONFIG_TARGET_T1040D4RDB)
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#define CFG_SYS_SGMII1_PHY_ADDR 0x01
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#elif defined(CONFIG_TARGET_T1042D4RDB)
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#define CFG_SYS_SGMII1_PHY_ADDR 0x02
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#define CFG_SYS_SGMII2_PHY_ADDR 0x03
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#define CFG_SYS_SGMII3_PHY_ADDR 0x01
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#endif
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#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
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#define CFG_SYS_RGMII1_PHY_ADDR 0x04
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#define CFG_SYS_RGMII2_PHY_ADDR 0x05
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#else
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#define CFG_SYS_RGMII1_PHY_ADDR 0x01
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#define CFG_SYS_RGMII2_PHY_ADDR 0x02
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#endif
|
|
|
|
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
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|
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
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|
#define CONFIG_VSC9953
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|
#ifdef CONFIG_TARGET_T1040RDB
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|
#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
|
|
#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
|
|
#else
|
|
#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
|
|
#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
|
|
#endif
|
|
#endif
|
|
#endif
|
|
|
|
/*
|
|
* Miscellaneous configurable options
|
|
*/
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 64 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
|
|
|
|
/*
|
|
* Dynamic MTD Partition support with mtdparts
|
|
*/
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
|
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
|
|
|
|
#define __USB_PHY_TYPE utmi
|
|
#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
|
|
|
|
#ifdef CONFIG_TARGET_T1040RDB
|
|
#define FDTFILE "t1040rdb/t1040rdb.dtb"
|
|
#elif defined(CONFIG_TARGET_T1042RDB_PI)
|
|
#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
|
|
#elif defined(CONFIG_TARGET_T1042RDB)
|
|
#define FDTFILE "t1042rdb/t1042rdb.dtb"
|
|
#elif defined(CONFIG_TARGET_T1040D4RDB)
|
|
#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
|
|
#elif defined(CONFIG_TARGET_T1042D4RDB)
|
|
#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
|
|
#endif
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
|
|
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
|
|
"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
|
"netdev=eth0\0" \
|
|
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
|
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
|
|
"tftpflash=tftpboot $loadaddr $uboot && " \
|
|
"protect off $ubootaddr +$filesize && " \
|
|
"erase $ubootaddr +$filesize && " \
|
|
"cp.b $loadaddr $ubootaddr $filesize && " \
|
|
"protect on $ubootaddr +$filesize && " \
|
|
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=2000000\0" \
|
|
"ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
|
|
"fdtaddr=1e00000\0" \
|
|
"fdtfile=" __stringify(FDTFILE) "\0" \
|
|
"bdev=sda3\0"
|
|
|
|
#include <asm/fsl_secure_boot.h>
|
|
|
|
#endif /* __CONFIG_H */
|