mirror of
https://github.com/AsahiLinux/u-boot
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60df809f62
This commit adds support for the B&R brsmarc1 SoM. The SoM is based on TI's AM335x SoC. Mainly vxWorks 6.9.4.x is running on the board, doing some PLC stuff on various carrier boards. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
168 lines
4 KiB
C
168 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for B&R BRSMARC1 Board
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*
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* Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/emif.h>
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#include <power/tps65217.h>
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#include "../common/bur_common.h"
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#include "../common/br_resetc.h"
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/* -------------------------------------------------------------------------*/
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/* -- defines for used GPIO Hardware -- */
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#define PER_RESET (2 * 32 + 0)
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SPL_BUILD)
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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static const struct ctrl_ioregs ddr3_ioregs = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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#define OSC (V_OSCK / 1000000)
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const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
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struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
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int rc;
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/*
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* enable additional clocks of modules which are accessed later from
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* VxWorks OS
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*/
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u32 *const clk_domains[] = { 0 };
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u32 *const clk_modules_specific[] = {
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&cmwkup->wkup_adctscctrl,
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&cmper->spi1clkctrl,
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&cmper->dcan0clkctrl,
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&cmper->dcan1clkctrl,
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&cmper->timer4clkctrl,
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&cmper->timer5clkctrl,
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&cmper->lcdclkctrl,
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&cmper->lcdcclkstctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_specific, 1);
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/* setup I2C */
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enable_i2c_pin_mux();
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/* peripheral reset */
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rc = gpio_request(PER_RESET, "PER_RESET");
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if (rc != 0)
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printf("cannot request PER_RESET GPIO!\n");
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rc = gpio_direction_output(PER_RESET, 0);
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if (rc != 0)
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printf("cannot set PER_RESET GPIO!\n");
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/* setup pmic */
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pmicsetup(0, 0);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr3;
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}
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void sdram_init(void)
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{
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config_ddr(400, &ddr3_ioregs,
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&ddr3_data,
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&ddr3_cmd_ctrl_data,
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&ddr3_emif_reg_data, 0);
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}
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#endif /* CONFIG_SPL_BUILD */
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#if !defined(CONFIG_SPL_BUILD)
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/* decision if backlight is switched on or not on powerup */
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int board_backlightstate(void)
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{
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u8 bklmask, rstcause;
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int rc = 0;
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rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
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rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
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if (rc != 0) {
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printf("%s: read rstctrl failed!\n", __func__);
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return 1;
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}
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if ((rstcause & bklmask) != 0)
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return 0;
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return 1;
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}
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/* Basic board specific setup. run quite after relocation */
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int board_init(void)
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{
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if (power_tps65217_init(0))
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printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
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return 0;
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}
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#if defined(CONFIG_BOARD_LATE_INIT)
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int board_late_init(void)
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{
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br_resetc_bmode();
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return 0;
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}
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#endif /* CONFIG_BOARD_LATE_INIT */
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#endif /* !CONFIG_SPL_BUILD */
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