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Curt Brune d7c865bdf2 MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register 
According to the MPC8555/MPC8541 reference manual the SS_EN (source
synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
during initialization.

>From section 9.4.1.8 of that manual:

   Source synchronous enable. This bit field must be set during
   initialization. See Section 9.6.1, "DDR SDRAM Initialization
   Sequence," details.

   0 - Reserved
   1 - The address and command are sent to the DDR SDRAMs source
       synchronously.

In addition, Freescale application note AN2805 is also very clear that
this bit must be set.

This patch reverts a change introduced by commit
457caecdbc.

Testing Done:

Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS
and inspected the generated assembly code to verify the SS_EN bit was being
set.  There is one extra instruction emitted:

  fff9b774: 65 29 80 00  oris    r9,r9,32768

Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
additional instructions were emitted related to this patch.

Booted an image on a MPC8541 based board successfully.

Signed-off-by: Curt Brune <curt@cumulusnetworks.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:28 -07:00
..
arm_ddr_gen3.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ctrl_regs.c MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register 2015-04-20 10:15:28 -07:00
ddr1_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ddr2_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ddr3_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ddr4_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
fsl_ddr_gen4.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
interactive.c driver/ddr/fsl: Fix tXP and tCKE 2014-09-25 08:36:18 -07:00
lc_common_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
main.c driver/ddr/fsl: Add sync of refresh 2015-02-24 13:09:42 -08:00
Makefile driver/ddr/fsl: Add DDR4 support to Freescale DDR driver 2014-04-22 17:58:48 -07:00
mpc85xx_ddr_gen1.c Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx 2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen2.c Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx 2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen3.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
mpc86xx_ddr.c Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx 2013-11-25 11:43:46 -08:00
options.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
util.c driver/ddr/fsl: Add sync of refresh 2015-02-24 13:09:42 -08:00