mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-10-04 05:12:13 +00:00
8ef07571a0
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
20 lines
537 B
ArmAsm
20 lines
537 B
ArmAsm
/*
|
|
* Copyright (c) 2014 Google, Inc
|
|
*
|
|
* From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
|
|
*
|
|
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
|
|
* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
|
|
* Copyright (C) 2007-2008 coresystems GmbH
|
|
* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0
|
|
*/
|
|
|
|
#include <common.h>
|
|
|
|
/* Note: ebp must not be touched in this code */
|
|
.globl car_init
|
|
car_init:
|
|
/* TODO: Add cache-as-RAM init here */
|
|
jmp car_init_ret
|