mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
d94604d558
Add support for lx2160a SoC -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEorkTmaQ1QAtDiYw67UVZlNoLnbQFAlwOzFoACgkQ7UVZlNoL nbQUdQ//SRRBfjUe8RYTbojvTGQav0GTxnMkz4GFSrqu0nvGMW2YSlheOMqq72sg rK5mQqDvdkItCn+G8AZ5NV2ijkQ7NQWCfqL3EtApzTpv6qjfgv7xvopz8q4NZvzB Wp+4cFf9YQjNwhJ7kLvWHB7SBiz9AfMYRAj9cscH9xsGL3HxPj62WDfwyK/QXana KIxRKQ26/1AdOZy272yv70vlFj4IwForxV3ACimsWRuYcb8yre3pE0tD7XpMCSNv 9GOfL7r4LS7U0+QnJoVeYLMhttRvOGJNUYtO2+ImO5NC3u9v8ehYEQ3FjGmM69CB vuPDQBDQc+Ap+Iu3k18PYSstp+mc9fbe9SQdlx6ARAecQqWTN4EOhf8s3m2bQq3S B58I0Zvowcdm8V2JKdXw94UqZX862U8PWH0BmcuX+4k+kRDwwU4XQY2nLp+Htz1w 2q6vEdKGj7YUOaomx9fmKRL+9BFGoD+M9mTiHOwzqwxy6Pa9VkruSvMErM7p2l/z xI/Q+xPJhyk5TXgZRsz4Nat59WpifWruibKEd4PArQ446heHWmzLWjw/MWiFyd/H agCdpDZVJ8R7h1Krs+Ez8XjR1Qcg0gs+CdNBuvqxzOpMQGGonXA1nwi8YfHykhII urfoC8pew1yxiLGw7J2JSX808HV/09WCSEsrOOhE3T78rXTDlS4= =aT7d -----END PGP SIGNATURE----- Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq Add TFA boot flow for some Layerscape platforms Add support for lx2160a SoC [trini: Add a bunch of missing MAINTAINERS entries] Signed-off-by: Tom Rini <trini@konsulko.com> |
||
---|---|---|
.. | ||
cpld.c | ||
cpld.h | ||
ddr.c | ||
ddr.h | ||
eth.c | ||
Kconfig | ||
ls1043ardb.c | ||
ls1043ardb_pbi.cfg | ||
ls1043ardb_rcw_nand.cfg | ||
ls1043ardb_rcw_sd.cfg | ||
MAINTAINERS | ||
Makefile | ||
README |
Overview -------- The LS1043A Reference Design Board (RDB) is a high-performance computing, evaluation, and development platform that supports the QorIQ LS1043A LayerScape Architecture processor. The LS1043ARDB provides SW development platform for the Freescale LS1043A processor series, with a complete debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. LS1043A SoC Overview -------------------- Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A SoC overview. LS1043ARDB board Overview ----------------------- - SERDES Connections, 4 lanes supporting: - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and standard PCIe card - QSGMII with x4 RJ45 connector - XFI with x1 RJ45 connector - DDR Controller - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s -IFC/Local Bus - One 128MB NOR flash 16-bit data bus - One 512 MB NAND flash with ECC support - CPLD connection - USB 3.0 - Two super speed USB 3.0 Type A ports - SDHC: connects directly to a full SD/MMC slot - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) - 4 I2C controllers - UART - Two 4-pin serial ports at up to 115.2 Kbit/s - Two DB9 D-Type connectors supporting one Serial port each - ARM JTAG support Memory map from core's view ---------------------------- Start Address End Address Description Size 0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB 0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB 0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB 0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB Booting Options --------------- a) NOR boot b) NAND boot c) SD boot