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https://github.com/AsahiLinux/u-boot
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b377d22264
Some Rockchip BROM versions (e.g. the RK3188 and RK3066) first read 1KB data from NAND into SRAM and executes it. Then, following a return to bootrom, the BROM loads additional code to SRAM (not overwriting the first block read) and reenters at the same address as the first time. To support booting either a TPL (on the RK3066) or SPL (on the RK3188) using this model of having to count entries, this commit adds code to the boot0 hook to track the number of entries and handle them accordingly. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
55 lines
1.9 KiB
C
55 lines
1.9 KiB
C
/*
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* Copyright 2017 Theobroma Systems Design und Consulting GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Execution starts on the instruction following this 4-byte header
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* (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This
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* magic constant will be written into the final image by the rkimage
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* tool, but we need to reserve space for it here.
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*
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* To make life easier for everyone, we build the SPL binary with
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* space for this 4-byte header already included in the binary.
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*/
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#ifdef CONFIG_SPL_BUILD
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/*
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* We need to add 4 bytes of space for the 'RK33' at the
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* beginning of the executable. However, as we want to keep
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* this generic and make it applicable to builds that are like
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* the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
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* TPL, but extra space needed in the SPL), we simply insert
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* a branch-to-next-instruction-word with the expectation that
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* the first one may be overwritten, if this is the first stage
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* contained in the final image created with mkimage)...
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*/
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b 1f /* if overwritten, entry-address is at the next word */
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1:
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#endif
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#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
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adr r3, entry_counter
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ldr r0, [r3]
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cmp r0, #1 /* check if entry_counter == 1 */
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beq reset /* regular bootup */
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add r0, #1
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str r0, [r3] /* increment the entry_counter in memory */
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mov r0, #0 /* return 0 to the BROM to signal 'OK' */
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bx lr /* return control to the BROM */
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entry_counter:
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.word 0
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#endif
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b reset
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#if !defined(CONFIG_ARM64)
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/*
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* For armv7, the addr '_start' will used as vector start address
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* and write to VBAR register, which needs to aligned to 0x20.
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*/
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.align(5), 0x0
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_start:
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ARM_VECTORS
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#endif
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#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
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.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
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#endif
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