Heinrich Schuchardt 6aabe229f8 riscv: define a cache line size for the generic CPU ... The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set. Define the cache line size for QEMU on RISC-V to be 64 bytes. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng@tinylab.org>		2023-07-24 13:22:24 +08:00
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cpu	riscv: define a cache line size for the generic CPU	2023-07-24 13:22:24 +08:00
dts	riscv: dts: jh7110: Add clock source from PLL	2023-07-24 13:21:06 +08:00
include/asm	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
lib	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
config.mk	riscv: Support CONFIG_REMAKE_ELF	2023-04-20 20:45:08 +08:00
Kconfig	riscv: t-head: licheepi4a: initial support added	2023-07-12 13:21:41 +08:00
Makefile	riscv: support building double-float modules	2022-10-20 15:22:21 +08:00