mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-16 16:23:14 +00:00
ea6de4ac80
Two support card variants are used with UniPhier reference boards: - 1 chip select support card (original CPLD) - 3 chip selects support card (ARIMA-compatible CPLD) Currently, the former is only supported on PH1-Pro4, but it can be expanded to PH1-LD4, PH1-sLD8 with a little code change. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/*
|
|
* Copyright (C) 2011-2015 Panasonic Corporation
|
|
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <mach/sbc-regs.h>
|
|
#include <mach/sg-regs.h>
|
|
|
|
void sbc_init(void)
|
|
{
|
|
u32 tmp;
|
|
|
|
/* system bus output enable */
|
|
tmp = readl(PC0CTRL);
|
|
tmp &= 0xfffffcff;
|
|
writel(tmp, PC0CTRL);
|
|
|
|
/* XECS1: sub/boot memory (boot swap = off/on) */
|
|
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
|
|
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
|
|
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
|
|
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
|
|
|
|
/* XECS0: boot/sub memory (boot swap = off/on) */
|
|
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
|
|
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
|
|
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
|
|
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
|
|
|
|
/* XECS3: peripherals */
|
|
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
|
|
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
|
|
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
|
|
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
|
|
|
|
/* base address regsiters */
|
|
writel(0x0000bc01, SBBASE0);
|
|
writel(0x0400bc01, SBBASE1);
|
|
writel(0x0800bf01, SBBASE3);
|
|
|
|
/* enable access to sub memory when boot swap is on */
|
|
if (boot_is_swapped())
|
|
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
|
|
|
|
sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
|
|
}
|