u-boot/arch/arm/dts/r8a77970-v3msk-u-boot.dts
Valentine Barshak 5f4e26964c ARM: renesas: Add R8A77970 V3MSK board and CPLD code
Add board code for the R8A77970 V3MSK board.
Add CPLD sysreset driver to the R-Car V3M SK board.
Extracted from a larger patch by Valentine Barshak.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync configs and board code with V3M Eagle, squash CPLD driver in]
2023-06-08 22:26:52 +02:00

65 lines
1.2 KiB
Text

// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the V3MSK board
*
* Copyright (C) 2019 Cogent Embedded, Inc.
*/
#include "r8a77970-v3msk.dts"
#include "r8a77970-u-boot.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
spi0 = &rpc;
};
cpld {
compatible = "renesas,v3msk-cpld";
status = "okay";
gpio-mdc = <&gpio1 21 0>;
gpio-mosi = <&gpio1 22 0>;
gpio-miso = <&gpio1 23 0>;
gpio-enablez = <&gpio1 19 0>;
/* Disable V3MSK Videobox Mini CANFD PHY */
gpios = <&gpio0 12 0>, <&gpio0 14 0>;
};
};
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
};
&phy0 {
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
&pfc {
avb0_pins: avb {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
};
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
reg = <0>;
status = "okay";
};
};