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https://github.com/AsahiLinux/u-boot
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ff50b323b3
The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
369 lines
14 KiB
C
369 lines
14 KiB
C
/*
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* Renesas R8A7795 CPG MSSR driver
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*
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* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on the following driver from Linux kernel:
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL3,
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CLK_PLL4,
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CLK_PLL1_DIV2,
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CLK_PLL1_DIV4,
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CLK_S0,
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CLK_S1,
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_SSPSRC,
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CLK_RINT,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a7795_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
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/* Core Clock Outputs */
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DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
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DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
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DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
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DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
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DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
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DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
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DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
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DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
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DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
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DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
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DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
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DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
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DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
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DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
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DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
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DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
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DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
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DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
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DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
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DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
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/* NOTE: HDMI, CSI, CAN etc. clock are missing */
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DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
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};
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static const struct mssr_mod_clk r8a7795_mod_clks[] = {
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DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
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DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
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DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
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DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
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DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
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DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
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DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
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DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
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DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
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DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
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DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
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DEF_MOD("cmt3", 300, R8A7795_CLK_R),
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DEF_MOD("cmt2", 301, R8A7795_CLK_R),
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DEF_MOD("cmt1", 302, R8A7795_CLK_R),
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DEF_MOD("cmt0", 303, R8A7795_CLK_R),
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DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
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DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
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DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
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DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
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DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
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DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
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DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
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DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
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DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
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DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
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DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
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DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
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DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
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DEF_MOD("rwdt", 402, R8A7795_CLK_R),
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DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
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DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
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DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
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DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
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DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
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DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
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DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
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DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
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DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
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DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
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DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
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DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
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DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
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DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
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DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
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DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
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DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
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DEF_MOD("thermal", 522, R8A7795_CLK_CP),
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DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
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DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
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DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
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DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
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DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
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DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
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DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
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DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
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DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
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DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
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DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
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DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
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DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
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DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
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DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
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DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
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DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
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DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
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DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
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DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
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DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
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DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
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DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
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DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
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DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
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DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
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DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
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DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
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DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
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DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
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DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
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DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
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DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
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DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
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DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
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DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
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DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
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DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
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DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
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DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
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DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
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DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
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DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
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DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
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DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
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DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
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DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
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DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
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DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
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DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
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DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
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DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
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DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
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DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
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DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
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DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
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DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
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DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
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DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
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DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
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DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
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DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
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DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
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DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
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DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
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DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
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DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
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DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
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DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
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DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
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DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
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DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
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DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
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DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
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DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
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DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
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DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
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DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
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DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
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DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
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DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
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DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
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DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
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};
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/*
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
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* 14 13 19 17 (MHz)
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*-------------------------------------------------------------------
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* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
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* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
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* 0 0 1 0 Prohibited setting
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* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
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* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
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* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
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* 0 1 1 0 Prohibited setting
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* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
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* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
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* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
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* 1 0 1 0 Prohibited setting
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* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
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* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
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* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
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* 1 1 1 0 Prohibited setting
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* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
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(((md) & BIT(13)) >> 11) | \
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(((md) & BIT(19)) >> 18) | \
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(((md) & BIT(17)) >> 17))
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static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
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/* EXTAL div PLL1 mult/div PLL3 mult/div */
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{ 1, 192, 1, 192, 1, },
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{ 1, 192, 1, 128, 1, },
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{ 0, /* Prohibited setting */ },
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{ 1, 192, 1, 192, 1, },
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{ 1, 160, 1, 160, 1, },
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{ 1, 160, 1, 106, 1, },
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{ 0, /* Prohibited setting */ },
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{ 1, 160, 1, 160, 1, },
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{ 1, 128, 1, 128, 1, },
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{ 1, 128, 1, 84, 1, },
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{ 0, /* Prohibited setting */ },
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{ 1, 128, 1, 128, 1, },
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{ 2, 192, 1, 192, 1, },
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{ 2, 192, 1, 128, 1, },
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{ 0, /* Prohibited setting */ },
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{ 2, 192, 1, 192, 1, },
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};
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static const struct mstp_stop_table r8a7795_mstp_table[] = {
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{ 0x00640800, 0x0, 0x00640800, 0 },
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{ 0xF3EE9390, 0x0, 0xF3EE9390, 0 },
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{ 0x340FAFDC, 0x2040, 0x340FAFDC, 0 },
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{ 0xD80C7CDF, 0x400, 0xD80C7CDF, 0 },
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{ 0x80000184, 0x180, 0x80000184, 0 },
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{ 0x40BFFF46, 0x0, 0x40BFFF46, 0 },
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{ 0xE5FBEECF, 0x0, 0xE5FBEECF, 0 },
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{ 0x39FFFF0E, 0x0, 0x39FFFF0E, 0 },
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{ 0x01F19FF4, 0x0, 0x01F19FF4, 0 },
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{ 0xFFDFFFFF, 0x0, 0xFFDFFFFF, 0 },
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{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
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{ 0x00000000, 0x0, 0x00000000, 0 },
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};
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static const void *r8a7795_get_pll_config(const u32 cpg_mode)
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{
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return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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}
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static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
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.core_clk = r8a7795_core_clks,
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.core_clk_size = ARRAY_SIZE(r8a7795_core_clks),
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.mod_clk = r8a7795_mod_clks,
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.mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks),
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.mstp_table = r8a7795_mstp_table,
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.mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table),
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.reset_node = "renesas,r8a7795-rst",
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.extalr_node = "extalr",
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.mod_clk_base = MOD_CLK_BASE,
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.clk_extal_id = CLK_EXTAL,
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.clk_extalr_id = CLK_EXTALR,
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.get_pll_config = r8a7795_get_pll_config,
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};
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static const struct udevice_id r8a7795_clk_ids[] = {
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{
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.compatible = "renesas,r8a7795-cpg-mssr",
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.data = (ulong)&r8a7795_cpg_mssr_info
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},
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{ }
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};
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U_BOOT_DRIVER(clk_r8a7795) = {
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.name = "clk_r8a7795",
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.id = UCLASS_CLK,
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.of_match = r8a7795_clk_ids,
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.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
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.ops = &gen3_clk_ops,
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.probe = gen3_clk_probe,
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.remove = gen3_clk_remove,
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};
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